Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Based on powerpc version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __ASM_MICROBLAZE_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __ASM_MICROBLAZE_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/pci-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCIBIOS_MIN_IO		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCIBIOS_MIN_MEM		0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Values for the `which' argument to sys_pciconfig_iobase syscall.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IOBASE_BRIDGE_NUMBER	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IOBASE_MEMORY		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IOBASE_IO		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IOBASE_ISA_IO		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IOBASE_ISA_MEM		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define pcibios_scan_all_fns(a, b)	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * Set this to 1 if you want the kernel to re-assign all PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * bus numbers (don't do that on ppc64 yet !)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define pcibios_assign_all_busses()	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) extern int pci_domain_nr(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Decide whether to display the domain number in /proc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern int pci_proc_domain(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct vm_area_struct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Tell PCI code what kind of PCI resource mappings we support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HAVE_PCI_MMAP			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ARCH_GENERIC_PCI_MMAP_RESOURCE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define arch_can_pci_mmap_io()		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			   size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			   size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 				      struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 				      enum pci_mmap_state mmap_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HAVE_PCI_LEGACY	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) extern void pcibios_resource_survey(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) extern pgprot_t	pci_phys_mem_access_prot(struct file *file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 					 unsigned long pfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 					 unsigned long size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 					 pgprot_t prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* This part of code was originally in xilinx-pci.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifdef CONFIG_PCI_XILINX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern void __init xilinx_pci_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline void __init xilinx_pci_init(void) { return; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif	/* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif /* __ASM_MICROBLAZE_PCI_H */