^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_MICROBLAZE_PCI_BRIDGE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_MICROBLAZE_PCI_BRIDGE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) extern struct list_head hose_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) extern int pcibios_vaddr_is_ioport(void __iomem *address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static inline int pcibios_vaddr_is_ioport(void __iomem *address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Structure of a PCI controller (host bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct pci_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) char is_dynamic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct list_head list_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct device *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int first_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int last_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int self_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *io_base_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) resource_size_t io_base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) resource_size_t pci_io_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Some machines (PReP) have a non 1:1 mapping of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * the PCI memory space in the CPU bus space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) resource_size_t pci_mem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Some machines have a special region to forward the ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * "memory" cycles such as VGA memory regions. Left to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * if unsupported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) resource_size_t isa_mem_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) resource_size_t isa_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct pci_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int __iomem *cfg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void __iomem *cfg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Used for variants of PCI indirect handling and possible quirks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * EXT_REG - provides access to PCI-e extended registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * to determine which bus number to match on when generating type0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * config cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * hanging if we don't have link and try to do config cycles to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * anything but the PHB. Only allow talking to the PHB if this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * BIG_ENDIAN - cfg_addr is a big endian register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * on the PLB4. Effectively disable MRM commands by setting this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define INDIRECT_TYPE_EXT_REG 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define INDIRECT_TYPE_BIG_ENDIAN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define INDIRECT_TYPE_BROKEN_MRM 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 indirect_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Currently, we limit ourselves to 1 IO range and 3 mem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * ranges since the common pci_bus structure can't handle more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct resource io_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct resource mem_resources[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int global_number; /* PCI domain number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline int isa_vaddr_is_ioport(void __iomem *address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* No specific ISA handling on ppc32 at this stage, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * all goes through PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* These are used for config access before all the PCI probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) has been done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) extern int early_read_config_byte(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int dev_fn, int where, u8 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) extern int early_read_config_word(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int dev_fn, int where, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) extern int early_read_config_dword(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int dev_fn, int where, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) extern int early_write_config_byte(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int dev_fn, int where, u8 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) extern int early_write_config_word(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int dev_fn, int where, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) extern int early_write_config_dword(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int dev_fn, int where, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) extern int early_find_capability(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int dev_fn, int cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) extern void setup_indirect_pci(struct pci_controller *hose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) resource_size_t cfg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) resource_size_t cfg_data, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Get the PCI host controller for an OF device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) extern struct pci_controller *pci_find_hose_for_OF_device(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Fill up host controller resources from the OF node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct device_node *dev, int primary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Allocate & free a PCI host bridge structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) extern void pcibios_free_controller(struct pci_controller *phb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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