^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008-2009 PetaLogix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Atmark Techno, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _ASM_MICROBLAZE_MMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _ASM_MICROBLAZE_MMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) # ifndef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) # include <asm-generic/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) # else /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) # ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) # ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Default "unsigned long" context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) typedef unsigned long mm_context_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Hardware Page Table Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) typedef struct _PTE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned long v:1; /* Entry is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned long vsid:24; /* Virtual segment identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned long h:1; /* Hash algorithm indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned long api:6; /* Abbreviated page index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned long rpn:20; /* Real (physical) page number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned long :3; /* Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned long r:1; /* Referenced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long c:1; /* Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long w:1; /* Write-thru cache mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned long i:1; /* Cache inhibited */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long m:1; /* Memory coherence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long g:1; /* Guarded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long :1; /* Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned long pp:2; /* Page protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) } PTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Values for PP (assumes Ks=0, Kp=1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) # define PP_RWXX 0 /* Supervisor read/write, User none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) # define PP_RWRX 1 /* Supervisor read/write, User read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) # define PP_RWRW 2 /* Supervisor read/write, User read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) # define PP_RXRX 3 /* Supervisor read, User read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Segment Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) typedef struct _SEGREG {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long t:1; /* Normal or I/O type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned long ks:1; /* Supervisor 'key' (normally 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long kp:1; /* User 'key' (normally 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long n:1; /* No-execute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long :4; /* Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long vsid:24; /* Virtual Segment Identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } SEGREG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) extern void _tlbia(void); /* invalidate all TLB entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * mapping has to increase tlb_skip size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) extern u32 tlb_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) # endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * instruction and data sides share a unified, 64-entry, semi-associative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * TLB which is maintained totally under software control. In addition, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * TLB which serves as a first level to the shared TLB. These two TLBs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * known as the UTLB and ITLB, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) # define MICROBLAZE_TLB_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* For cases when you want to skip some TLB entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) # define MICROBLAZE_TLB_SKIP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Use the last TLB for temporary access to LMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) # define MICROBLAZE_LMB_TLB_ID 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * TLB entries are defined by a "high" tag portion and a "low" data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * portion. The data portion is 32-bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * TLB entries are managed entirely under software control by reading,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * writing, and searching using the MTS and MFS instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) # define TLB_LO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) # define TLB_HI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) # define TLB_DATA TLB_LO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) # define TLB_TAG TLB_HI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Tag portion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) # define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) # define TLB_PAGESZ_MASK 0x00000380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) # define TLB_PAGESZ(x) (((x) & 0x7) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) # define PAGESZ_1K 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) # define PAGESZ_4K 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) # define PAGESZ_16K 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) # define PAGESZ_64K 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) # define PAGESZ_256K 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) # define PAGESZ_1M 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) # define PAGESZ_4M 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) # define PAGESZ_16M 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) # define TLB_VALID 0x00000040 /* Entry is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Data portion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) # define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) # define TLB_PERM_MASK 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) # define TLB_EX 0x00000200 /* Instruction execution allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) # define TLB_WR 0x00000100 /* Writes permitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) # define TLB_ZSEL_MASK 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) # define TLB_ZSEL(x) (((x) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) # define TLB_ATTR_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) # define TLB_W 0x00000008 /* Caching is write-through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) # define TLB_I 0x00000004 /* Caching is inhibited */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) # define TLB_M 0x00000002 /* Memory is coherent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) # define TLB_G 0x00000001 /* Memory is guarded from prefetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) # endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) # endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif /* _ASM_MICROBLAZE_MMU_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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