^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007-2009 PetaLogix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * based on v850 version which was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2001,02,03 NEC Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _ASM_MICROBLAZE_CACHEFLUSH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _ASM_MICROBLAZE_CACHEFLUSH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Somebody depends on this; sigh... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Look at Documentation/core-api/cachetlb.rst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Cache handling functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Microblaze has a write-through data cache, meaning that the data cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * never needs to be flushed. The only flushing operations that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * implemented are to invalidate the instruction cache. These are called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * after loading a user application into memory, we must invalidate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * instruction cache to make sure we don't fetch old, bad code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* struct cache, d=dcache, i=icache, fl = flush, iv = invalidate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * suffix r = range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct scache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* icache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void (*ie)(void); /* enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void (*id)(void); /* disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void (*ifl)(void); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void (*iflr)(unsigned long a, unsigned long b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void (*iin)(void); /* invalidate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void (*iinr)(unsigned long a, unsigned long b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* dcache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void (*de)(void); /* enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void (*dd)(void); /* disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void (*dfl)(void); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void (*dflr)(unsigned long a, unsigned long b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void (*din)(void); /* invalidate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void (*dinr)(unsigned long a, unsigned long b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* microblaze cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) extern struct scache *mbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void microblaze_cache_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define enable_icache() mbc->ie();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define disable_icache() mbc->id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define flush_icache() mbc->ifl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define flush_icache_range(start, end) mbc->iflr(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define invalidate_icache() mbc->iin();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define invalidate_icache_range(start, end) mbc->iinr(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define enable_dcache() mbc->de();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define disable_dcache() mbc->dd();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* FIXME for LL-temac driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define invalidate_dcache() mbc->din();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define invalidate_dcache_range(start, end) mbc->dinr(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define flush_dcache() mbc->dfl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define flush_dcache_range(start, end) mbc->dflr(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* MS: We have to implement it because of rootfs-jffs2 issue on WB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define flush_dcache_page(page) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long addr = (unsigned long) page_address(page); /* virtual */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) addr = (u32)virt_to_phys((void *)addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) flush_dcache_range((unsigned) (addr), (unsigned) (addr) + PAGE_SIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define flush_cache_page(vma, vmaddr, pfn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) flush_dcache_range(pfn << PAGE_SHIFT, (pfn << PAGE_SHIFT) + PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline void copy_to_user_page(struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct page *page, unsigned long vaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void *dst, void *src, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 addr = virt_to_phys(dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) memcpy(dst, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (vma->vm_flags & VM_EXEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) invalidate_icache_range(addr, addr + PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) flush_dcache_range(addr, addr + PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define copy_to_user_page copy_to_user_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #include <asm-generic/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif /* _ASM_MICROBLAZE_CACHEFLUSH_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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