^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Device Tree Generator version: 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) Copyright 2007-2008 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) Copyright 2007-2009 Michal Simek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Michal SIMEK <monstr@monstr.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * CAUTION: This file is automatically generated by libgen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /dts-v1/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) compatible = "xlnx,microblaze";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) model = "testing";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) DDR2_SDRAM: memory@90000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) device_type = "memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) reg = < 0x90000000 0x10000000 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) aliases {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ethernet0 = &Hard_Ethernet_MAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) serial0 = &RS232_Uart_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) chosen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) bootargs = "console=ttyUL0,115200 highres=on";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) stdout-path = "/plb@0/serial@84000000";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #cpus = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) microblaze_0: cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) clock-frequency = <125000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) compatible = "xlnx,microblaze-7.10.d";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) d-cache-baseaddr = <0x90000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) d-cache-highaddr = <0x9fffffff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) d-cache-line-size = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) d-cache-size = <0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) i-cache-baseaddr = <0x90000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) i-cache-highaddr = <0x9fffffff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) i-cache-line-size = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) i-cache-size = <0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) model = "microblaze,7.10.d";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) timebase-frequency = <125000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) xlnx,addr-tag-bits = <0xf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) xlnx,allow-dcache-wr = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) xlnx,allow-icache-wr = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) xlnx,area-optimized = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) xlnx,cache-byte-size = <0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) xlnx,d-lmb = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) xlnx,d-opb = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) xlnx,d-plb = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) xlnx,data-size = <0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) xlnx,dcache-addr-tag = <0xf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) xlnx,dcache-always-used = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) xlnx,dcache-byte-size = <0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) xlnx,dcache-line-len = <0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) xlnx,dcache-use-fsl = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) xlnx,debug-enabled = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) xlnx,div-zero-exception = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) xlnx,dopb-bus-exception = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) xlnx,dynamic-bus-sizing = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) xlnx,edge-is-positive = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) xlnx,family = "virtex5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) xlnx,endianness = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) xlnx,fpu-exception = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) xlnx,fsl-data-size = <0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) xlnx,fsl-exception = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) xlnx,fsl-links = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) xlnx,i-lmb = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) xlnx,i-opb = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) xlnx,i-plb = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) xlnx,icache-always-used = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) xlnx,icache-line-len = <0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) xlnx,icache-use-fsl = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) xlnx,ill-opcode-exception = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) xlnx,instance = "microblaze_0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) xlnx,interconnect = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) xlnx,interrupt-is-edge = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) xlnx,iopb-bus-exception = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) xlnx,mmu-dtlb-size = <0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) xlnx,mmu-itlb-size = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) xlnx,mmu-tlb-access = <0x3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) xlnx,mmu-zones = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) xlnx,number-of-pc-brk = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) xlnx,number-of-rd-addr-brk = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) xlnx,number-of-wr-addr-brk = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) xlnx,opcode-0x0-illegal = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) xlnx,pvr = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) xlnx,pvr-user1 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) xlnx,pvr-user2 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) xlnx,reset-msr = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) xlnx,sco = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) xlnx,unaligned-exceptions = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) xlnx,use-barrel = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) xlnx,use-dcache = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) xlnx,use-div = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) xlnx,use-ext-brk = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) xlnx,use-ext-nm-brk = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) xlnx,use-extended-fsl-instr = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) xlnx,use-fpu = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) xlnx,use-hw-mul = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) xlnx,use-icache = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) xlnx,use-interrupt = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) xlnx,use-mmu = <0x3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) xlnx,use-msr-instr = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) xlnx,use-pcmp-instr = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mb_plb: plb@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ranges ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) FLASH: flash@a0000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bank-width = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg = < 0xa0000000 0x2000000 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) xlnx,family = "virtex5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) xlnx,include-datawidth-matching-0 = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) xlnx,include-datawidth-matching-1 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) xlnx,include-datawidth-matching-2 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) xlnx,include-datawidth-matching-3 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) xlnx,include-negedge-ioregs = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) xlnx,include-plb-ipif = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) xlnx,include-wrbuf = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) xlnx,max-mem-width = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) xlnx,mch-native-dwidth = <0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) xlnx,mch-plb-clk-period-ps = <0x1f40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) xlnx,mch-splb-awidth = <0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) xlnx,mch0-accessbuf-depth = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) xlnx,mch0-protocol = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) xlnx,mch0-rddatabuf-depth = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) xlnx,mch1-accessbuf-depth = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) xlnx,mch1-protocol = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) xlnx,mch1-rddatabuf-depth = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) xlnx,mch2-accessbuf-depth = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) xlnx,mch2-protocol = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) xlnx,mch2-rddatabuf-depth = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) xlnx,mch3-accessbuf-depth = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) xlnx,mch3-protocol = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) xlnx,mch3-rddatabuf-depth = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) xlnx,mem0-width = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) xlnx,mem1-width = <0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) xlnx,mem2-width = <0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) xlnx,mem3-width = <0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) xlnx,num-banks-mem = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) xlnx,num-channels = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) xlnx,priority-mode = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) xlnx,synch-mem-0 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) xlnx,synch-mem-1 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) xlnx,synch-mem-2 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) xlnx,synch-mem-3 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) xlnx,synch-pipedelay-0 = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) xlnx,synch-pipedelay-1 = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) xlnx,synch-pipedelay-2 = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) xlnx,synch-pipedelay-3 = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) xlnx,tavdv-ps-mem-0 = <0x1adb0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) xlnx,tavdv-ps-mem-1 = <0x3a98>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) xlnx,tavdv-ps-mem-2 = <0x3a98>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) xlnx,tavdv-ps-mem-3 = <0x3a98>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) xlnx,tcedv-ps-mem-0 = <0x1adb0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) xlnx,tcedv-ps-mem-1 = <0x3a98>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) xlnx,tcedv-ps-mem-2 = <0x3a98>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) xlnx,tcedv-ps-mem-3 = <0x3a98>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) xlnx,thzce-ps-mem-0 = <0x88b8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) xlnx,thzce-ps-mem-1 = <0x1b58>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) xlnx,thzce-ps-mem-2 = <0x1b58>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) xlnx,thzce-ps-mem-3 = <0x1b58>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) xlnx,thzoe-ps-mem-0 = <0x1b58>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) xlnx,thzoe-ps-mem-1 = <0x1b58>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) xlnx,thzoe-ps-mem-2 = <0x1b58>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) xlnx,thzoe-ps-mem-3 = <0x1b58>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) xlnx,tlzwe-ps-mem-0 = <0x88b8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) xlnx,tlzwe-ps-mem-1 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) xlnx,tlzwe-ps-mem-2 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) xlnx,tlzwe-ps-mem-3 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) xlnx,twc-ps-mem-0 = <0x2af8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) xlnx,twc-ps-mem-1 = <0x3a98>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) xlnx,twc-ps-mem-2 = <0x3a98>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) xlnx,twc-ps-mem-3 = <0x3a98>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) xlnx,twp-ps-mem-0 = <0x11170>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) xlnx,twp-ps-mem-1 = <0x2ee0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) xlnx,twp-ps-mem-2 = <0x2ee0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) xlnx,twp-ps-mem-3 = <0x2ee0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) xlnx,xcl0-linesize = <0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) xlnx,xcl0-writexfer = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) xlnx,xcl1-linesize = <0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) xlnx,xcl1-writexfer = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) xlnx,xcl2-linesize = <0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) xlnx,xcl2-writexfer = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) xlnx,xcl3-linesize = <0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) xlnx,xcl3-writexfer = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) compatible = "xlnx,compound";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ranges ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ethernet@81c00000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) interrupt-parent = <&xps_intc_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) interrupts = < 5 2 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) llink-connected = <&PIM3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) local-mac-address = [ 00 0a 35 00 00 00 ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg = < 0x81c00000 0x40 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) xlnx,bus2core-clk-ratio = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) xlnx,phy-type = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) xlnx,phyaddr = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) xlnx,rxcsum = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) xlnx,rxfifo = <0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) xlnx,temac-type = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) xlnx,txcsum = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) xlnx,txfifo = <0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) IIC_EEPROM: i2c@81600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) compatible = "xlnx,xps-iic-2.00.a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) interrupt-parent = <&xps_intc_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) interrupts = < 6 2 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) reg = < 0x81600000 0x10000 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) xlnx,clk-freq = <0x7735940>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) xlnx,family = "virtex5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) xlnx,gpo-width = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) xlnx,iic-freq = <0x186a0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) xlnx,scl-inertial-delay = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) xlnx,sda-inertial-delay = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) xlnx,ten-bit-adr = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) LEDs_8Bit: gpio@81400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) compatible = "xlnx,xps-gpio-1.00.a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) interrupt-parent = <&xps_intc_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) interrupts = < 7 2 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) reg = < 0x81400000 0x10000 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) xlnx,all-inputs = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) xlnx,all-inputs-2 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) xlnx,dout-default = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) xlnx,dout-default-2 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) xlnx,family = "virtex5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) xlnx,gpio-width = <0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) xlnx,interrupt-present = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) xlnx,is-bidir = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) xlnx,is-bidir-2 = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) xlnx,is-dual = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) xlnx,tri-default = <0xffffffff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) xlnx,tri-default-2 = <0xffffffff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) gpio-leds {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) compatible = "gpio-leds";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) heartbeat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) label = "Heartbeat";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) gpios = <&LEDs_8Bit 4 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) linux,default-trigger = "heartbeat";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) yellow {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) label = "Yellow";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) gpios = <&LEDs_8Bit 5 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) red {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) label = "Red";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) gpios = <&LEDs_8Bit 6 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) green {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) label = "Green";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) gpios = <&LEDs_8Bit 7 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) gpio-restart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) compatible = "gpio-restart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * FIXME: is this active low or active high?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * the current flag (1) indicates active low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * delay measures are templates, should be adjusted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * to datasheet or trial-and-error with real hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) gpios = <&LEDs_8Bit 2 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) active-delay = <100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) inactive-delay = <10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) wait-delay = <100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) RS232_Uart_1: serial@84000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clock-frequency = <125000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) compatible = "xlnx,xps-uartlite-1.00.a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) current-speed = <115200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) device_type = "serial";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) interrupt-parent = <&xps_intc_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) interrupts = < 8 0 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) port-number = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) reg = < 0x84000000 0x10000 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) xlnx,baudrate = <0x1c200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) xlnx,data-bits = <0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) xlnx,family = "virtex5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) xlnx,odd-parity = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) xlnx,use-parity = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) SysACE_CompactFlash: sysace@83600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) compatible = "xlnx,xps-sysace-1.00.a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) interrupt-parent = <&xps_intc_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) interrupts = < 4 2 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) reg = < 0x83600000 0x10000 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) xlnx,family = "virtex5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) xlnx,mem-width = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) debug_module: debug@84400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) compatible = "xlnx,mdm-1.00.d";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) reg = < 0x84400000 0x10000 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) xlnx,family = "virtex5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) xlnx,interconnect = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) xlnx,jtag-chain = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) xlnx,mb-dbg-ports = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) xlnx,uart-width = <0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) xlnx,use-uart = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) xlnx,write-fsl-ports = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mpmc@90000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) compatible = "xlnx,mpmc-4.02.a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ranges ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PIM3: sdma@84600180 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) compatible = "xlnx,ll-dma-1.00.a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) interrupt-parent = <&xps_intc_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) interrupts = < 2 2 1 2 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) reg = < 0x84600180 0x80 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) xps_intc_0: interrupt-controller@81800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #interrupt-cells = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) compatible = "xlnx,xps-intc-1.00.a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) interrupt-controller ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) reg = < 0x81800000 0x10000 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) xlnx,kind-of-intr = <0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) xlnx,num-intr-inputs = <0x9>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) xps_timer_1: timer@83c00000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) compatible = "xlnx,xps-timer-1.00.a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) interrupt-parent = <&xps_intc_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) interrupts = < 3 2 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) reg = < 0x83c00000 0x10000 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) xlnx,count-width = <0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) xlnx,family = "virtex5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) xlnx,gen0-assert = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) xlnx,gen1-assert = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) xlnx,one-timer-only = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) xlnx,trig0-assert = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) xlnx,trig1-assert = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } ;
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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