^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/m68k/mvme16x/config.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1995 Richard Hirst [richard@sleepie.demon.co.uk]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * linux/amiga/config.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 1993 Hamish Macdonald
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * License. See the file README.legal in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/major.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/genhd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/bootinfo-vme.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/mvme16xhw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) extern t_bdid mvme_bdid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static MK48T08ptr_t volatile rtc = (MK48T08ptr_t)MVME_RTC_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void mvme16x_get_model(char *model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) extern void mvme16x_sched_init(irq_handler_t handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) extern int mvme16x_hwclk (int, struct rtc_time *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) extern void mvme16x_reset (void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int bcd2int (unsigned char b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned short mvme16x_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) EXPORT_SYMBOL(mvme16x_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int __init mvme16x_parse_bootinfo(const struct bi_record *bi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) uint16_t tag = be16_to_cpu(bi->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (tag == BI_VME_TYPE || tag == BI_VME_BRDINFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void mvme16x_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pr_info("\r\n\nCalled mvme16x_reset\r\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* The string of returns is to delay the reset until the whole
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * message is output. Assert reset bit in GCSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *(volatile char *)0xfff40107 = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void mvme16x_get_model(char *model)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) p_bdid p = &mvme_bdid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) char suf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) suf[1] = p->brdsuffix[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) suf[2] = p->brdsuffix[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) suf[3] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) suf[0] = suf[1] ? '-' : '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) sprintf(model, "Motorola MVME%x%s", be16_to_cpu(p->brdno), suf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void mvme16x_get_hardware_list(struct seq_file *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) uint16_t brdno = be16_to_cpu(mvme_bdid.brdno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (brdno == 0x0162 || brdno == 0x0172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned char rev = *(unsigned char *)MVME162_VERSION_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) seq_printf (m, "VMEchip2 %spresent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rev & MVME16x_CONFIG_NO_VMECHIP2 ? "NOT " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) seq_printf (m, "SCSI interface %spresent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) rev & MVME16x_CONFIG_NO_SCSICHIP ? "NOT " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) seq_printf (m, "Ethernet i/f %spresent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) rev & MVME16x_CONFIG_NO_ETHERNET ? "NOT " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * This function is called during kernel startup to initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * the mvme16x IRQ handling routines. Should probably ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * that the base vectors for the VMEChip2 and PCCChip2 are valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void __init mvme16x_init_IRQ (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) m68k_setup_user_interrupt(VEC_USER, 192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCC2CHIP (0xfff42000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCCSCCMICR (PCC2CHIP + 0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PCCSCCTICR (PCC2CHIP + 0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCCSCCRICR (PCC2CHIP + 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCCTPIACKR (PCC2CHIP + 0x25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef CONFIG_EARLY_PRINTK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /**** cd2401 registers ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CD2401_ADDR (0xfff45000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CyGFRCR (0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CyCCR (0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CyCLR_CHAN (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CyINIT_CHAN (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CyCHIP_RESET (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CyENB_XMTR (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CyDIS_XMTR (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CyENB_RCVR (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CyDIS_RCVR (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CyCAR (0xee)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CyIER (0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CyMdmCh (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CyRxExc (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CyRxData (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CyTxMpty (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CyTxRdy (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CyLICR (0x26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CyRISR (0x89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CyTIMEOUT (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CySPECHAR (0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CyOVERRUN (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CyPARITY (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CyFRAME (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CyBREAK (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CyREOIR (0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CyTEOIR (0x85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CyMEOIR (0x86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CyNOTRANS (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CyRFOC (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CyRDR (0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CyTDR (0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CyMISR (0x8b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CyRISR (0x89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CyTISR (0x8a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CyMSVR1 (0xde)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CyMSVR2 (0xdf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CyDSR (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CyDCD (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CyCTS (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CyDTR (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CyRTS (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CyRTPRL (0x25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CyRTPRH (0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CyCOR1 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CyPARITY_NONE (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CyPARITY_E (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CyPARITY_O (0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define Cy_5_BITS (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define Cy_6_BITS (0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define Cy_7_BITS (0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define Cy_8_BITS (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CyCOR2 (0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CyETC (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CyCtsAE (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CyCOR3 (0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define Cy_1_STOP (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define Cy_2_STOP (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CyCOR4 (0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CyREC_FIFO (0x0F) /* Receive FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CyCOR5 (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CyCOR6 (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CyCOR7 (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CyRBPR (0xcb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CyRCOR (0xc8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CyTBPR (0xc3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CyTCOR (0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CySCHR1 (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CySCHR2 (0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CyTPR (0xda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CyPILR1 (0xe3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CyPILR2 (0xe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CyPILR3 (0xe1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CyCMR (0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CyASYNC (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CyLICR (0x26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CyLIVR (0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CySCRL (0x23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CySCRH (0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CyTFTC (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void mvme16x_cons_write(struct console *co, const char *str, unsigned count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) volatile unsigned char *base_addr = (u_char *)CD2401_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) volatile u_char sink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u_char ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u_char do_lf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Ensure transmitter is enabled! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) base_addr[CyCAR] = (u_char)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) while (base_addr[CyCCR])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) base_addr[CyCCR] = CyENB_XMTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ier = base_addr[CyIER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) base_addr[CyIER] = CyTxMpty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (in_8(PCCSCCTICR) & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* We have a Tx int. Acknowledge it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) sink = in_8(PCCTPIACKR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if ((base_addr[CyLICR] >> 2) == port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (i == count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Last char of string is now output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) base_addr[CyTEOIR] = CyNOTRANS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (do_lf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) base_addr[CyTDR] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) str++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) do_lf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) else if (*str == '\n') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) base_addr[CyTDR] = '\r';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) do_lf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) base_addr[CyTDR] = *str++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) base_addr[CyTEOIR] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) base_addr[CyTEOIR] = CyNOTRANS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) base_addr[CyIER] = ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void __init config_mvme16x(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) p_bdid p = &mvme_bdid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) char id[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) uint16_t brdno = be16_to_cpu(p->brdno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) mach_max_dma_address = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mach_sched_init = mvme16x_sched_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mach_init_IRQ = mvme16x_init_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mach_hwclk = mvme16x_hwclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mach_reset = mvme16x_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mach_get_model = mvme16x_get_model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mach_get_hardware_list = mvme16x_get_hardware_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Report board revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (strncmp("BDID", p->bdid, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pr_crit("Bug call .BRD_ID returned garbage - giving up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Board type is only set by newer versions of vmelilo/tftplilo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (vme_brdtype == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) vme_brdtype = brdno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mvme16x_get_model(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pr_info("BRD_ID: %s BUG %x.%x %02x/%02x/%02x\n", id, p->rev >> 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) p->rev & 0xf, p->yr, p->mth, p->day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (brdno == 0x0162 || brdno == 0x172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned char rev = *(unsigned char *)MVME162_VERSION_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mvme16x_config = rev | MVME16x_CONFIG_GOT_SCCA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pr_info("MVME%x Hardware status:\n", brdno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pr_info(" CPU Type 68%s040\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) rev & MVME16x_CONFIG_GOT_FPU ? "" : "LC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pr_info(" CPU clock %dMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) rev & MVME16x_CONFIG_SPEED_32 ? 32 : 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pr_info(" VMEchip2 %spresent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) rev & MVME16x_CONFIG_NO_VMECHIP2 ? "NOT " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pr_info(" SCSI interface %spresent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) rev & MVME16x_CONFIG_NO_SCSICHIP ? "NOT " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pr_info(" Ethernet interface %spresent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) rev & MVME16x_CONFIG_NO_ETHERNET ? "NOT " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mvme16x_config = MVME16x_CONFIG_GOT_LP | MVME16x_CONFIG_GOT_CD2401;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static irqreturn_t mvme16x_abort_int (int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned long *new = (unsigned long *)vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long *old = (unsigned long *)0xffe00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) volatile unsigned char uc, *ucp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) uint16_t brdno = be16_to_cpu(mvme_bdid.brdno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (brdno == 0x0162 || brdno == 0x172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ucp = (volatile unsigned char *)0xfff42043;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) uc = *ucp | 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *ucp = uc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *(volatile unsigned long *)0xfff40074 = 0x40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *(new+4) = *(old+4); /* Illegal instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) *(new+9) = *(old+9); /* Trace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *(new+47) = *(old+47); /* Trap #15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (brdno == 0x0162 || brdno == 0x172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *(new+0x5e) = *(old+0x5e); /* ABORT switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) *(new+0x6e) = *(old+0x6e); /* ABORT switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static u64 mvme16x_read_clk(struct clocksource *cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct clocksource mvme16x_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .name = "pcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .rating = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .read = mvme16x_read_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .mask = CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static u32 clk_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define PCC_TIMER_CLOCK_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define PCC_TIMER_CYCLES (PCC_TIMER_CLOCK_FREQ / HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PCCTCMP1 (PCC2CHIP + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define PCCTCNT1 (PCC2CHIP + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PCCTOVR1 (PCC2CHIP + 0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define PCCTIC1 (PCC2CHIP + 0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define PCCTOVR1_TIC_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define PCCTOVR1_COC_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define PCCTOVR1_OVR_CLR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PCCTIC1_INT_LEVEL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PCCTIC1_INT_CLR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define PCCTIC1_INT_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static irqreturn_t mvme16x_timer_int (int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) irq_handler_t timer_routine = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) out_8(PCCTOVR1, PCCTOVR1_OVR_CLR | PCCTOVR1_TIC_EN | PCCTOVR1_COC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) out_8(PCCTIC1, PCCTIC1_INT_EN | PCCTIC1_INT_CLR | PCCTIC1_INT_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) clk_total += PCC_TIMER_CYCLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) timer_routine(0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) void mvme16x_sched_init (irq_handler_t timer_routine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) uint16_t brdno = be16_to_cpu(mvme_bdid.brdno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Using PCCchip2 or MC2 chip tick timer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (request_irq(MVME16x_IRQ_TIMER, mvme16x_timer_int, IRQF_TIMER, "timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) timer_routine))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) panic ("Couldn't register timer int");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) out_be32(PCCTCNT1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) out_be32(PCCTCMP1, PCC_TIMER_CYCLES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) out_8(PCCTOVR1, PCCTOVR1_OVR_CLR | PCCTOVR1_TIC_EN | PCCTOVR1_COC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) out_8(PCCTIC1, PCCTIC1_INT_EN | PCCTIC1_INT_CLR | PCCTIC1_INT_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) clocksource_register_hz(&mvme16x_clk, PCC_TIMER_CLOCK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (brdno == 0x0162 || brdno == 0x172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) irq = MVME162_IRQ_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) irq = MVME167_IRQ_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (request_irq(irq, mvme16x_abort_int, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "abort", mvme16x_abort_int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) panic ("Couldn't register abort int");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static u64 mvme16x_read_clk(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u8 overflow, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tmp = in_8(PCCTOVR1) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ticks = in_be32(PCCTCNT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) overflow = in_8(PCCTOVR1) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (overflow != tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ticks = in_be32(PCCTCNT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ticks += overflow * PCC_TIMER_CYCLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ticks += clk_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int bcd2int (unsigned char b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ((b>>4)*10 + (b&15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int mvme16x_hwclk(int op, struct rtc_time *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #warning check me!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) rtc->ctrl = RTC_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) t->tm_year = bcd2int (rtc->bcd_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) t->tm_mon = bcd2int(rtc->bcd_mth) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) t->tm_mday = bcd2int (rtc->bcd_dom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) t->tm_hour = bcd2int (rtc->bcd_hr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) t->tm_min = bcd2int (rtc->bcd_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) t->tm_sec = bcd2int (rtc->bcd_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) rtc->ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (t->tm_year < 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) t->tm_year += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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