^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/m68k/mvme147/config.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1996 Dave Frascone [chaos@mindspring.com]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Cloned from Richard Hirst [richard@sleepie.demon.co.uk]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1993 Hamish Macdonald
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * License. See the file README.legal in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/major.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/genhd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/bootinfo-vme.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/mvme147hw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void mvme147_get_model(char *model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) extern void mvme147_sched_init(irq_handler_t handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) extern int mvme147_hwclk (int, struct rtc_time *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern void mvme147_reset (void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int bcd2int (unsigned char b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int __init mvme147_parse_bootinfo(const struct bi_record *bi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) uint16_t tag = be16_to_cpu(bi->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (tag == BI_VME_TYPE || tag == BI_VME_BRDINFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void mvme147_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pr_info("\r\n\nCalled mvme147_reset\r\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) m147_pcc->watchdog = 0x0a; /* Clear timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) m147_pcc->watchdog = 0xa5; /* Enable watchdog - 100ms to reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void mvme147_get_model(char *model)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) sprintf(model, "Motorola MVME147");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * This function is called during kernel startup to initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * the mvme147 IRQ handling routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void __init mvme147_init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) m68k_setup_user_interrupt(VEC_USER, 192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void __init config_mvme147(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mach_max_dma_address = 0x01000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mach_sched_init = mvme147_sched_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mach_init_IRQ = mvme147_init_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mach_hwclk = mvme147_hwclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mach_reset = mvme147_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mach_get_model = mvme147_get_model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Board type is only set by newer versions of vmelilo/tftplilo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!vme_brdtype)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) vme_brdtype = VME_TYPE_MVME147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static u64 mvme147_read_clk(struct clocksource *cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct clocksource mvme147_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = "pcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .rating = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .read = mvme147_read_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .mask = CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static u32 clk_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCC_TIMER_CLOCK_FREQ 160000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCC_TIMER_CYCLES (PCC_TIMER_CLOCK_FREQ / HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PCC_TIMER_PRELOAD (0x10000 - PCC_TIMER_CYCLES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Using pcc tick timer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static irqreturn_t mvme147_timer_int (int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) irq_handler_t timer_routine = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) m147_pcc->t1_cntrl = PCC_TIMER_CLR_OVF | PCC_TIMER_COC_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PCC_TIMER_TIC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) m147_pcc->t1_int_cntrl = PCC_INT_ENAB | PCC_TIMER_INT_CLR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PCC_LEVEL_TIMER1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) clk_total += PCC_TIMER_CYCLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) timer_routine(0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void mvme147_sched_init (irq_handler_t timer_routine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (request_irq(PCC_IRQ_TIMER1, mvme147_timer_int, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "timer 1", timer_routine))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pr_err("Couldn't register timer interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Init the clock with a value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* The clock counter increments until 0xFFFF then reloads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) m147_pcc->t1_preload = PCC_TIMER_PRELOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) m147_pcc->t1_cntrl = PCC_TIMER_CLR_OVF | PCC_TIMER_COC_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PCC_TIMER_TIC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) m147_pcc->t1_int_cntrl = PCC_INT_ENAB | PCC_TIMER_INT_CLR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PCC_LEVEL_TIMER1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) clocksource_register_hz(&mvme147_clk, PCC_TIMER_CLOCK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static u64 mvme147_read_clk(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 overflow, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u16 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tmp = m147_pcc->t1_cntrl >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) count = m147_pcc->t1_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) overflow = m147_pcc->t1_cntrl >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (overflow != tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) count = m147_pcc->t1_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) count -= PCC_TIMER_PRELOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ticks = count + overflow * PCC_TIMER_CYCLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ticks += clk_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int bcd2int (unsigned char b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ((b>>4)*10 + (b&15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int mvme147_hwclk(int op, struct rtc_time *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #warning check me!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) m147_rtc->ctrl = RTC_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) t->tm_year = bcd2int (m147_rtc->bcd_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) t->tm_mon = bcd2int(m147_rtc->bcd_mth) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) t->tm_mday = bcd2int (m147_rtc->bcd_dom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) t->tm_hour = bcd2int (m147_rtc->bcd_hr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) t->tm_min = bcd2int (m147_rtc->bcd_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) t->tm_sec = bcd2int (m147_rtc->bcd_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) m147_rtc->ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (t->tm_year < 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) t->tm_year += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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