Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * fp_decode.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright Roman Zippel, 1997.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *    notice, and the entire permission notice in its entirety,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *    including the disclaimer of warranties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *    notice, this list of conditions and the following disclaimer in the
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * 3. The name of the author may not be used to endorse or promote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *    products derived from this software without specific prior
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *    written permission.
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * the GNU General Public License, in which case the provisions of the GPL are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * required INSTEAD OF the above restrictions.  (This clause is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * necessary due to a potential bad interaction between the GPL and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * the restrictions contained in a BSD-style copyright.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #ifndef _FP_DECODE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define _FP_DECODE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* These macros do the dirty work of the instr decoding, several variables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * can be defined in the source file to modify the work of these macros,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * currently the following variables are used:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * The register usage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * d0 - will contain source operand for data direct mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *	otherwise scratch register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * d1 - upper 16bit are reserved for caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *	lower 16bit may contain further arguments,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  *	is destroyed during decoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * d2 - contains first two instruction words,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  *	first word will be used for extension word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * a0 - will point to source/dest operand for any indirect mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  *	otherwise scratch register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * a1 - scratch register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * a2 - base addr to the task structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * the current implementation doesn't check for every disallowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * addressing mode (e.g. pc relative modes as destination), as long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * as it only means a new addressing mode, which should not appear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * in a program and that doesn't crash the emulation, I think it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * not a problem to allow these modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) do_fmovem=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) do_fmovem_cr=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) do_no_pc_mode=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) do_fscc=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) | first decoding of the instr type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) | this separates the conditional instr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) .macro	fp_decode_cond_instr_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	bfextu	%d2{#8,#2},%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	jmp	([0f:w,%pc,%d0*4])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) |	.long	"f<op>","fscc/fdbcc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) |	.long	"fbccw","fbccl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) | second decoding of the instr type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) | this separates most move instr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) .macro	fp_decode_move_instr_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	bfextu	%d2{#16,#3},%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	jmp	([0f:w,%pc,%d0*4])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) |	.long	"f<op> fpx,fpx","invalid instr"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) |	.long	"f<op> <ea>,fpx","fmove fpx,<ea>"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) |	.long	"fmovem <ea>,fpcr","fmovem <ea>,fpx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) |	.long	"fmovem fpcr,<ea>","fmovem fpx,<ea>"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) | extract the source specifier, specifies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) | either source fp register or data format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) .macro	fp_decode_sourcespec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	bfextu	%d2{#19,#3},%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) | decode destination format for fmove reg,ea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .macro	fp_decode_dest_format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	bfextu	%d2{#19,#3},%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) | decode source register for fmove reg,ea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .macro	fp_decode_src_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	bfextu	%d2{#22,#3},%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) | extract the addressing mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) | it depends on the instr which of the modes is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .macro	fp_decode_addr_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	bfextu	%d2{#10,#3},%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	jmp	([0f:w,%pc,%d0*4])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) |	.long	"data register direct","addr register direct"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) |	.long	"addr register indirect"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) |	.long	"addr register indirect postincrement"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) |	.long	"addr register indirect predecrement"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) |	.long	"addr register + index16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) |	.long	"extension mode1","extension mode2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) | extract the register for the addressing mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .macro	fp_decode_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	bfextu	%d2{#13,#3},%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) | decode the 8bit displacement from the brief extension word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .macro	fp_decode_disp8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	move.b	%d2,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	ext.w	%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) | decode the index of the brief/full extension word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .macro	fp_decode_index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	bfextu	%d2{#17,#3},%d0		| get the register nr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	btst	#15,%d2			| test for data/addr register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	jne	1\@f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	printf	PDECODE,"d%d",1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	jsr	fp_get_data_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	jra	2\@f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 1\@:	printf	PDECODE,"a%d",1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	jsr	fp_get_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	move.l	%a0,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 2\@:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) debug	lea	"'l'.w,%a0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	btst	#11,%d2			| 16/32 bit size?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	jne	3\@f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) debug	lea	"'w'.w,%a0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ext.l	%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 3\@:	printf	PDECODE,":%c",1,%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	move.w	%d2,%d1			| scale factor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	rol.w	#7,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	and.w	#3,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) debug	move.l	"%d1,-(%sp)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) debug	ext.l	"%d1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	printf	PDECODE,":%d",1,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) debug	move.l	"(%sp)+,%d1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	lsl.l	%d1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) | decode the base displacement size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .macro	fp_decode_basedisp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	bfextu	%d2{#26,#2},%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	jmp	([0f:w,%pc,%d0*4])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) |	.long	"reserved","null displacement"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) |	.long	"word displacement","long displacement"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .macro	fp_decode_outerdisp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	bfextu	%d2{#30,#2},%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	jmp	([0f:w,%pc,%d0*4])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) |	.long	"no memory indirect action/reserved","null outer displacement"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) |	.long	"word outer displacement","long outer displacement"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) | get the extension word and test for brief or full extension type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .macro	fp_get_test_extword label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	fp_get_instr_word %d2,fp_err_ua1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	btst	#8,%d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	jne	\label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) | test if %pc is the base register for the indirect addr mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .macro	fp_test_basereg_d16	label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	btst	#20,%d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	jeq	\label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) | test if %pc is the base register for one of the extended modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .macro	fp_test_basereg_ext	label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	btst	#19,%d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	jeq	\label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .macro	fp_test_suppr_index label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	btst	#6,%d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	jne	\label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) | addressing mode: data register direct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .macro	fp_mode_data_direct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	fp_decode_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	printf	PDECODE,"d%d",1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) | addressing mode: address register indirect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .macro	fp_mode_addr_indirect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	fp_decode_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	printf	PDECODE,"(a%d)",1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	jsr	fp_get_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) | adjust stack for byte moves from/to stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .macro	fp_test_sp_byte_move
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.if	!do_fmovem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.if	do_fscc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	move.w	#6,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	cmp.w	#7,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	jne	1\@f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.if	!do_fscc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	cmp.w	#6,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	jne	1\@f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	move.w	#4,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 1\@:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) | addressing mode: address register indirect with postincrement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .macro	fp_mode_addr_indirect_postinc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	fp_decode_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	printf	PDECODE,"(a%d)+",1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	fp_test_sp_byte_move
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	jsr	fp_get_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	move.l	%a0,%a1			| save addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.if	do_fmovem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	lea	(%a0,%d1.w*4),%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.if	!do_fmovem_cr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	lea	(%a0,%d1.w*8),%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	add.w	(fp_datasize,%d1.w*2),%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	jsr	fp_put_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	move.l	%a1,%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) | addressing mode: address register indirect with predecrement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .macro	fp_mode_addr_indirect_predec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	fp_decode_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	printf	PDECODE,"-(a%d)",1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	fp_test_sp_byte_move
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	jsr	fp_get_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.if	do_fmovem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.if	!do_fmovem_cr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	lea	(-12,%a0),%a1		| setup to addr of 1st reg to move
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	neg.w	%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	lea	(%a0,%d1.w*4),%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	add.w	%d1,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	lea	(%a0,%d1.w*4),%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	jsr	fp_put_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	move.l	%a1,%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	neg.w	%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	lea	(%a0,%d1.w*4),%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	jsr	fp_put_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	sub.w	(fp_datasize,%d1.w*2),%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	jsr	fp_put_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) | addressing mode: address register/programm counter indirect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) |		   with 16bit displacement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .macro	fp_mode_addr_indirect_disp16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.if	!do_no_pc_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	fp_test_basereg_d16 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	printf	PDECODE,"pc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	fp_get_pc %a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	jra	2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 1:	fp_decode_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	printf	PDECODE,"a%d",1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	jsr	fp_get_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 2:	fp_get_instr_word %a1,fp_err_ua1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	printf	PDECODE,"@(%x)",1,%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	add.l	%a1,%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) | perform preindex (if I/IS == 0xx and xx != 00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .macro	fp_do_preindex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	moveq	#3,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	and.w	%d2,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	jeq	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	btst	#2,%d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	jne	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	printf	PDECODE,")@("
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	getuser.l (%a1),%a1,fp_err_ua1,%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) debug	jra	"2f"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 1:	printf	PDECODE,","
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) | perform postindex (if I/IS == 1xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .macro	fp_do_postindex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	btst	#2,%d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	jeq	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	printf	PDECODE,")@("
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	getuser.l (%a1),%a1,fp_err_ua1,%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) debug	jra	"2f"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 1:	printf	PDECODE,","
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) | all other indirect addressing modes will finally end up here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .macro	fp_mode_addr_indirect_extmode0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.if	!do_no_pc_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	fp_test_basereg_ext 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	printf	PDECODE,"pc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	fp_get_pc %a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	jra	2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 1:	fp_decode_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	printf	PDECODE,"a%d",1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	jsr	fp_get_addr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 2:	move.l	%a0,%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	swap	%d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	fp_get_test_extword 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	| addressing mode: address register/programm counter indirect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	|		   with index and 8bit displacement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	fp_decode_disp8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) debug	ext.l	"%d0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	printf	PDECODE,"@(%x,",1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	add.w	%d0,%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	fp_decode_index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	add.l	%d0,%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	printf	PDECODE,")"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	jra	9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 3:	| addressing mode: address register/programm counter memory indirect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	|		   with base and/or outer displacement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	btst	#7,%d2			| base register suppressed?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	jeq	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	printf	PDECODE,"!"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	sub.l	%a1,%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 1:	printf	PDECODE,"@("
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	fp_decode_basedisp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	.long	fp_ill,1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	.long	2f,3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #ifdef FPU_EMU_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 1:	printf	PDECODE,"0"		| null base displacement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	jra	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 2:	fp_get_instr_word %a0,fp_err_ua1 | 16bit base displacement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	printf	PDECODE,"%x:w",1,%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	jra	4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 3:	fp_get_instr_long %a0,fp_err_ua1 | 32bit base displacement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	printf	PDECODE,"%x:l",1,%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 4:	add.l	%a0,%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	fp_do_postindex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	fp_test_suppr_index 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	fp_decode_index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	add.l	%d0,%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 1:	fp_do_preindex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	fp_decode_outerdisp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	.long	5f,1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	.long	2f,3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #ifdef FPU_EMU_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 1:	printf	PDECODE,"0"		| null outer displacement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	jra	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 2:	fp_get_instr_word %a0,fp_err_ua1 | 16bit outer displacement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	printf	PDECODE,"%x:w",1,%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	jra	4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 3:	fp_get_instr_long %a0,fp_err_ua1 | 32bit outer displacement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	printf	PDECODE,"%x:l",1,%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 4:	add.l	%a0,%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 5:	printf	PDECODE,")"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 9:	move.l	%a1,%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	swap	%d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) | get the absolute short address from user space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .macro	fp_mode_abs_short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	fp_get_instr_word %a0,fp_err_ua1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	printf	PDECODE,"%x.w",1,%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) | get the absolute long address from user space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .macro	fp_mode_abs_long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	fp_get_instr_long %a0,fp_err_ua1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	printf	PDECODE,"%x.l",1,%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #endif /* _FP_DECODE_H */