^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* libgcc1 routines for 68000 w/o floating-point hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Copyright (C) 1994, 1996, 1997, 1998 Free Software Foundation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) This file is part of GNU CC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) GNU CC is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Free Software Foundation; either version 2, or (at your option) any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) In addition to the permissions in the GNU General Public License, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Free Software Foundation gives you unlimited permission to link the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) compiled version of this file with other programs, and to distribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) those programs without any restriction coming from the use of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) file. (The General Public License restrictions do apply in other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) respects; for example, they cover modification of the file, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) distribution when not linked into another program.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) This file is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) General Public License for more details. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* As a special exception, if you link this library with files
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) compiled with GCC to produce an executable, this does not cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) the resulting executable to be covered by the GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) This exception does not however invalidate any other reasons why
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) the executable file might be covered by the GNU General Public License. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Use this one for any 680x0; assumes no floating point hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) The trailing " '" appearing on some lines is for ANSI preprocessors. Yuk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Some of this code comes from MINIX, via the folks at ericsson.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) D. V. Henkel-Wallace (gumby@cygnus.com) Fete Bastille, 1992
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* These are predefined by new versions of GNU cpp. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifndef __USER_LABEL_PREFIX__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define __USER_LABEL_PREFIX__ _
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifndef __REGISTER_PREFIX__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define __REGISTER_PREFIX__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifndef __IMMEDIATE_PREFIX__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define __IMMEDIATE_PREFIX__ #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* ANSI concatenation macros. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CONCAT1(a, b) CONCAT2(a, b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CONCAT2(a, b) a ## b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Use the right prefix for global labels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Use the right prefix for registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Use the right prefix for immediate values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMM(x) CONCAT1 (__IMMEDIATE_PREFIX__, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define d0 REG (d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define d1 REG (d1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define d2 REG (d2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define d3 REG (d3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define d4 REG (d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define d5 REG (d5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define d6 REG (d6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define d7 REG (d7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define a0 REG (a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define a1 REG (a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define a2 REG (a2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define a3 REG (a3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define a4 REG (a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define a5 REG (a5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define a6 REG (a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define fp REG (fp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define sp REG (sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .proc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .globl SYM (__udivsi3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SYM (__udivsi3):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #if !(defined(__mcf5200__) || defined(__mcoldfire__))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) movel d2, sp@-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) movel sp@(12), d1 /* d1 = divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) movel sp@(8), d0 /* d0 = dividend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) cmpl IMM (0x10000), d1 /* divisor >= 2 ^ 16 ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) jcc L3 /* then try next algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) movel d0, d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clrw d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) swap d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) divu d1, d2 /* high quotient in lower word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) movew d2, d0 /* save high quotient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) swap d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) movew sp@(10), d2 /* get low dividend + high rest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) divu d1, d2 /* low quotient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) movew d2, d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) jra L6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) L3: movel d1, d2 /* use d2 as divisor backup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) L4: lsrl IMM (1), d1 /* shift divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) lsrl IMM (1), d0 /* shift dividend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cmpl IMM (0x10000), d1 /* still divisor >= 2 ^ 16 ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) jcc L4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) divu d1, d0 /* now we have 16 bit divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) andl IMM (0xffff), d0 /* mask out divisor, ignore remainder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Multiply the 16 bit tentative quotient with the 32 bit divisor. Because of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) the operand ranges, this might give a 33 bit product. If this product is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) greater than the dividend, the tentative quotient was too large. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) movel d2, d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mulu d0, d1 /* low part, 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) swap d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mulu d0, d2 /* high part, at most 17 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) swap d2 /* align high part with low part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) tstw d2 /* high part 17 bits? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) jne L5 /* if 17 bits, quotient was too large */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) addl d2, d1 /* add parts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) jcs L5 /* if sum is 33 bits, quotient was too large */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) cmpl sp@(8), d1 /* compare the sum with the dividend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) jls L6 /* if sum > dividend, quotient was too large */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) L5: subql IMM (1), d0 /* adjust quotient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) L6: movel sp@+, d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #else /* __mcf5200__ || __mcoldfire__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Coldfire implementation of non-restoring division algorithm from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) Hennessy & Patterson, Appendix A. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) link a6,IMM (-12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) moveml d2-d4,sp@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) movel a6@(8),d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) movel a6@(12),d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clrl d2 | clear p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) moveq IMM (31),d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) L1: addl d0,d0 | shift reg pair (p,a) one bit left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) addxl d2,d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) movl d2,d3 | subtract b from p, store in tmp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) subl d1,d3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) jcs L2 | if no carry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bset IMM (0),d0 | set the low order bit of a to 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) movl d3,d2 | and store tmp in p.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) L2: subql IMM (1),d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) jcc L1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) moveml sp@,d2-d4 | restore data registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unlk a6 | and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif /* __mcf5200__ || __mcoldfire__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) EXPORT_SYMBOL(__udivsi3)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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