^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pci.c -- basic PCI support code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * From arch/i386/kernel/pci-i386.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * We need to avoid collisions with `mirrored' VGA ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * and other strange ISA hardware, so we always want the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * addresses to be allocated in the 0x000-0x0ff region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * modulo 0x400.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Why? Because some silly external IO cards only decode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * the low 10 bits of the IO address. The 0x00-0xff region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * is reserved for motherboard devices that decode all 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * but we want to try to avoid allocating at 0x2900-0x2bff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * which might be mirrored at 0x0100-0x03ff..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) resource_size_t pcibios_align_resource(void *data, const struct resource *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) resource_size_t size, resource_size_t align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) resource_size_t start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if ((res->flags & IORESOURCE_IO) && (start & 0x300))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) start = (start + 0x3ff) & ~0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) start = (start + align - 1) & ~(align - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * This is taken from the ARM code for this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int pcibios_enable_device(struct pci_dev *dev, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u16 cmd, newcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) pci_read_config_word(dev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) newcmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) for (idx = 0; idx < 6; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Only set up the requested stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (!(mask & (1 << idx)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) r = dev->resource + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (!r->start && r->end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pr_err("PCI: Device %s not available because of resource collisions\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (r->flags & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) newcmd |= PCI_COMMAND_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (r->flags & IORESOURCE_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) newcmd |= PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Bridges (eg, cardbus bridges) need to be fully enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (newcmd != cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pr_info("PCI: enabling device %s (0x%04x -> 0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pci_name(dev), cmd, newcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pci_write_config_word(dev, PCI_COMMAND, newcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void pcibios_fixup_bus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) char *pcibios_setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags