^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/include/asm/traps.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1993 Hamish Macdonald
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _M68K_TRAPS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _M68K_TRAPS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) typedef void (*e_vector)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) extern e_vector vectors[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) extern e_vector *_ramvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) asmlinkage void auto_inthandler(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) asmlinkage void user_inthandler(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) asmlinkage void bad_inthandler(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VEC_RESETSP (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VEC_RESETPC (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VEC_BUSERR (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VEC_ADDRERR (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VEC_ILLEGAL (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VEC_ZERODIV (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VEC_CHK (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VEC_TRAP (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VEC_PRIV (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VEC_TRACE (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VEC_LINE10 (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VEC_LINE11 (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VEC_RESV12 (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VEC_COPROC (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VEC_FORMAT (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VEC_UNINT (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VEC_RESV16 (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VEC_RESV17 (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VEC_RESV18 (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VEC_RESV19 (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VEC_RESV20 (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VEC_RESV21 (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VEC_RESV22 (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VEC_RESV23 (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VEC_SPUR (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VEC_INT1 (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VEC_INT2 (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VEC_INT3 (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VEC_INT4 (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VEC_INT5 (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VEC_INT6 (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VEC_INT7 (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VEC_SYS (32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VEC_TRAP1 (33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VEC_TRAP2 (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VEC_TRAP3 (35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VEC_TRAP4 (36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VEC_TRAP5 (37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VEC_TRAP6 (38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VEC_TRAP7 (39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VEC_TRAP8 (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VEC_TRAP9 (41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VEC_TRAP10 (42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VEC_TRAP11 (43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VEC_TRAP12 (44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VEC_TRAP13 (45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VEC_TRAP14 (46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VEC_TRAP15 (47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VEC_FPBRUC (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define VEC_FPIR (49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VEC_FPDIVZ (50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VEC_FPUNDER (51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VEC_FPOE (52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VEC_FPOVER (53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VEC_FPNAN (54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define VEC_FPUNSUP (55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define VEC_MMUCFG (56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define VEC_MMUILL (57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define VEC_MMUACC (58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VEC_RESV59 (59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define VEC_UNIMPEA (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VEC_UNIMPII (61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VEC_RESV62 (62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define VEC_RESV63 (63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define VEC_USER (64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define VECOFF(vec) ((vec)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Status register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PS_T (0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PS_S (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PS_M (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PS_C (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* bits for 68020/68030 special status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define FC (0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define FB (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RC (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RB (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DF (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RM (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RW (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SZ (0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DFC (0x0007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* bits for 68030 MMU status register (mmusr,psr) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MMU_B (0x8000) /* bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MMU_L (0x4000) /* limit violation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MMU_S (0x2000) /* supervisor violation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MMU_WP (0x0800) /* write-protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MMU_I (0x0400) /* invalid descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MMU_M (0x0200) /* ATC entry modified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MMU_T (0x0040) /* transparent translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MMU_NUM (0x0007) /* number of levels traversed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* bits for 68040 special status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CP_040 (0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CU_040 (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CT_040 (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CM_040 (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MA_040 (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ATC_040 (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LK_040 (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RW_040 (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SIZ_040 (0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TT_040 (0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TM_040 (0x0007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* bits for 68040 write back status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define WBV_040 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define WBSIZ_040 (0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define WBBYT_040 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define WBWRD_040 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define WBLNG_040 (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define WBTT_040 (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define WBTM_040 (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* bus access size codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define BA_SIZE_BYTE (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define BA_SIZE_WORD (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define BA_SIZE_LONG (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define BA_SIZE_LINE (0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* bus access transfer type codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define BA_TT_MOVE16 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* bits for 68040 MMU status register (mmusr) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MMU_B_040 (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MMU_G_040 (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MMU_S_040 (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MMU_CM_040 (0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MMU_M_040 (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MMU_WP_040 (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MMU_T_040 (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MMU_R_040 (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* bits in the 68060 fault status long word (FSLW) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MMU060_MA (0x08000000) /* misaligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MMU060_LK (0x02000000) /* locked transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MMU060_RW (0x01800000) /* read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) # define MMU060_RW_W (0x00800000) /* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) # define MMU060_RW_R (0x01000000) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) # define MMU060_RW_RMW (0x01800000) /* read/modify/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) # define MMU060_W (0x00800000) /* general write, includes rmw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MMU060_SIZ (0x00600000) /* transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MMU060_TT (0x00180000) /* transfer type (TT) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MMU060_TM (0x00070000) /* transfer modifier (TM) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MMU060_IO (0x00008000) /* instruction or operand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MMU060_PBE (0x00004000) /* push buffer bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MMU060_SBE (0x00002000) /* store buffer bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MMU060_PTA (0x00001000) /* pointer A fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MMU060_PTB (0x00000800) /* pointer B fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MMU060_IL (0x00000400) /* double indirect descr fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MMU060_PF (0x00000200) /* page fault (invalid descr) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MMU060_SP (0x00000100) /* supervisor protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MMU060_WP (0x00000080) /* write protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MMU060_TWE (0x00000040) /* bus error on table search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MMU060_RE (0x00000020) /* bus error on read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MMU060_WE (0x00000010) /* bus error on write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MMU060_TTR (0x00000008) /* error caused by TTR translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MMU060_BPE (0x00000004) /* branch prediction error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MMU060_SEE (0x00000001) /* software emulated error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* cases of missing or invalid descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MMU060_DESC_ERR (MMU060_PTA | MMU060_PTB | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MMU060_IL | MMU060_PF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* bits that indicate real errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | MMU060_SP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MMU060_WP | MMU060_TWE | MMU060_RE | MMU060_WE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* structure for stack frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct pt_regs ptregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned long iaddr; /* instruction address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } fmt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long effaddr; /* effective address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } fmt3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned long effaddr; /* effective address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned long pc; /* pc of faulted instr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) } fmt4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned long effaddr; /* effective address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned short ssw; /* special status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned short wb3s; /* write back 3 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned short wb2s; /* write back 2 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned short wb1s; /* write back 1 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long faddr; /* fault address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned long wb3a; /* write back 3 address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned long wb3d; /* write back 3 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long wb2a; /* write back 2 address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long wb2d; /* write back 2 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned long wb1a; /* write back 1 address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned long wb1dpd0; /* write back 1 data/push data 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long pd1; /* push data 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned long pd2; /* push data 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long pd3; /* push data 3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } fmt7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned long iaddr; /* instruction address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned short int1[4]; /* internal registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) } fmt9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned short int1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned short ssw; /* special status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned short isc; /* instruction stage c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned short isb; /* instruction stage b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long daddr; /* data cycle fault address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned short int2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned long dobuf; /* data cycle output buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned short int3[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } fmta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned short int1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned short ssw; /* special status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned short isc; /* instruction stage c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned short isb; /* instruction stage b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned long daddr; /* data cycle fault address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned short int2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned long dobuf; /* data cycle output buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned short int3[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned long baddr; /* stage B address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned short int4[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned long dibuf; /* data cycle input buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned short int5[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned ver : 4; /* stack frame version # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int6:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned short int7[18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) } fmtb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #endif /* _M68K_TRAPS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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