Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* sun3xflop.h: Sun3/80 specific parts of the floppy driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Derived partially from asm-sparc/floppy.h, which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *     Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Sun3x version 2/4/2000 Sam Creasey (sammy@sammy.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef __ASM_SUN3X_FLOPPY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define __ASM_SUN3X_FLOPPY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/sun3x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* default interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SUN3X_FDC_IRQ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* some constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define FCR_TC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define FCR_EJECT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define FCR_MTRON 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define FCR_DSEL1 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define FCR_DSEL0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* We don't need no stinkin' I/O port allocation crap. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #undef release_region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #undef request_region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define release_region(X, Y)	do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define request_region(X, Y, Z)	(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) struct sun3xflop_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	volatile unsigned char *status_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	volatile unsigned char *data_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	volatile unsigned char *fcr_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	volatile unsigned char *fvr_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned char fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) } sun3x_fdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* Super paranoid... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #undef HAVE_DISABLE_HLT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* Routines unique to each controller type on a Sun. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static unsigned char sun3x_82072_fd_inb(int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	static int once = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) //	udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	switch(port & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		pr_crit("floppy: Asked to read unknown port %d\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		panic("floppy: Port bolixed.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	case 4: /* FD_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return (*sun3x_fdc.status_r) & ~STATUS_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	case 5: /* FD_DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		return (*sun3x_fdc.data_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	case 7: /* FD_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		/* ugly hack, I can't find a way to actually detect the disk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		if(!once) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			once = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			return 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	panic("sun_82072_fd_inb: How did I get here?");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static void sun3x_82072_fd_outb(unsigned char value, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) //	udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	switch(port & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		pr_crit("floppy: Asked to write to unknown port %d\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		panic("floppy: Port bolixed.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	case 2: /* FD_DOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		/* Oh geese, 82072 on the Sun has no DOR register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		 * so we make do with taunting the FCR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		 * ASSUMPTIONS:  There will only ever be one floppy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		 *               drive attached to a Sun controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		 *               and it will be at drive zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		unsigned char fcr = sun3x_fdc.fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		if(value & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			fcr |= (FCR_DSEL0 | FCR_MTRON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			fcr &= ~(FCR_DSEL0 | FCR_MTRON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		if(fcr != sun3x_fdc.fcr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			*(sun3x_fdc.fcr_r) = fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			sun3x_fdc.fcr = fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	case 5: /* FD_DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		*(sun3x_fdc.data_r) = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	case 7: /* FD_DCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		*(sun3x_fdc.status_r) = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	case 4: /* FD_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		*(sun3x_fdc.status_r) = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) asmlinkage irqreturn_t sun3xflop_hardint(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	register unsigned char st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #undef TRACE_FLPY_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define NO_FLOPPY_ASSEMBLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #ifdef TRACE_FLPY_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	static int calls=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	static int bytes=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	static int dma_wait=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if(!doing_pdma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		floppy_interrupt(irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) //	pr_info("doing pdma\n");// st %x\n", sun_fdc->status_82072);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #ifdef TRACE_FLPY_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if(!calls)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		bytes = virtual_dma_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		register int lcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		register char *lptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		    lcount; lcount--, lptr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*			st=fd_inb(virtual_dma_port+4) & 0x80 ;  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			st = *(sun3x_fdc.status_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*			if(st != 0xa0)                  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*				break;                  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			if((st & 0x80) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				virtual_dma_count = lcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				virtual_dma_addr = lptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			if((st & 0x20) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			if(virtual_dma_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*				fd_outb(*lptr, virtual_dma_port+5); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				*(sun3x_fdc.data_r) = *lptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*				*lptr = fd_inb(virtual_dma_port+5); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				*lptr = *(sun3x_fdc.data_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		virtual_dma_count = lcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		virtual_dma_addr = lptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*		st = fd_inb(virtual_dma_port+4);   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		st = *(sun3x_fdc.status_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #ifdef TRACE_FLPY_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	calls++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) //	pr_info("st=%02x\n", st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if(st == 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if(!(st & 0x20)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		virtual_dma_residue += virtual_dma_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		virtual_dma_count=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		doing_pdma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #ifdef TRACE_FLPY_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		pr_info("count=%x, residue=%x calls=%d bytes=%x dma_wait=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			virtual_dma_count, virtual_dma_residue, calls, bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			dma_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		calls = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		dma_wait=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		floppy_interrupt(irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #ifdef TRACE_FLPY_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if(!virtual_dma_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		dma_wait++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int sun3xflop_request_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	static int once = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if(!once) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		once = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		error = request_irq(FLOPPY_IRQ, sun3xflop_hardint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				    0, "floppy", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return ((error == 0) ? 0 : -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	} else return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void __init floppy_set_flags(int *ints,int param, int param2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int sun3xflop_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if(FLOPPY_IRQ < 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		FLOPPY_IRQ = SUN3X_FDC_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	sun3x_fdc.status_r = (volatile unsigned char *)SUN3X_FDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	sun3x_fdc.data_r  = (volatile unsigned char *)(SUN3X_FDC+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	sun3x_fdc.fcr_r = (volatile unsigned char *)SUN3X_FDC_FCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	sun3x_fdc.fvr_r = (volatile unsigned char *)SUN3X_FDC_FVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	sun3x_fdc.fcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	/* Last minute sanity check... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if(*sun3x_fdc.status_r == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	*sun3x_fdc.fvr_r = FLOPPY_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	*sun3x_fdc.fcr_r = FCR_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	*sun3x_fdc.fcr_r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/* Success... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	floppy_set_flags(NULL, 1, FD_BROKEN_DCL); // I don't know how to detect this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	allowed_drive_mask = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	return (int) SUN3X_FDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* I'm not precisely sure this eject routine works */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int sun3x_eject(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if(MACH_IS_SUN3X) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		sun3x_fdc.fcr |= (FCR_DSEL0 | FCR_EJECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		*(sun3x_fdc.fcr_r) = sun3x_fdc.fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		sun3x_fdc.fcr &= ~(FCR_DSEL0 | FCR_EJECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		*(sun3x_fdc.fcr_r) = sun3x_fdc.fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define fd_eject(drive) sun3x_eject()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #endif /* !(__ASM_SUN3X_FLOPPY_H) */