^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * nettel.h -- Lineo (formerly Moreton Bay) NETtel support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 1999-2000, Moreton Bay (www.moretonbay.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright 2000-2001, Lineo Inc. (www.lineo.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (C) Copyright 2001-2002, SnapGear Inc., (www.snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef nettel_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define nettel_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifdef CONFIG_NETtel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #ifdef CONFIG_COLDFIRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*---------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #if defined(CONFIG_M5307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * NETtel/5307 based hardware first. DTR/DCD lines are wired to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * GPIO lines. Most of the LED's are driver through a latch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * connected to CS2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCFPP_DCD1 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCFPP_DCD0 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCFPP_DTR1 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MCFPP_DTR0 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NETtel_LEDADDR 0x30400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) extern volatile unsigned short ppdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * These functions defined to give quasi generic access to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * PPIO bits used for DTR/DCD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static __inline__ unsigned int mcf_getppdata(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) volatile unsigned short *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pp = (volatile unsigned short *) MCFSIM_PADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return((unsigned int) *pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) volatile unsigned short *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pp = (volatile unsigned short *) MCFSIM_PADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ppdata = (ppdata & ~mask) | bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *pp = ppdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*---------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #elif defined(CONFIG_M5206e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * NETtel/5206e based hardware has leds on latch on CS3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * No support modem for lines??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define NETtel_LEDADDR 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*---------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #elif defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * NETtel/5272 based hardware. DTR/DCD lines are wired to GPB lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MCFPP_DCD0 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MCFPP_DCD1 0x0000 /* Port 1 no DCD support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MCFPP_DTR0 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MCFPP_DTR1 0x0000 /* Port 1 no DTR support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * These functions defined to give quasi generic access to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * PPIO bits used for DTR/DCD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static __inline__ unsigned int mcf_getppdata(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return readw(MCFSIM_PBDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writew((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*---------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif /* CONFIG_NETtel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif /* nettel_h */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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