^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _M68K_MVME16xHW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _M68K_MVME16xHW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) u_char ack_icr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) flt_icr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) sel_icr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) pe_icr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) bsy_icr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) spare1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) cr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) spare2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) spare3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) spare4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) } MVMElp, *MVMElpPtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MVME_LPR_BASE 0xfff42030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define mvmelp ((*(volatile MVMElpPtr)(MVME_LPR_BASE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) bcd_sec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) bcd_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) bcd_hr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) bcd_dow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) bcd_dom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) bcd_mth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bcd_year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) } MK48T08_t, *MK48T08ptr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RTC_WRITE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RTC_READ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RTC_STOP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MVME_RTC_BASE 0xfffc1ff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MVME_I596_BASE 0xfff46000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MVME_SCC_A_ADDR 0xfff45005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MVME_SCC_B_ADDR 0xfff45001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MVME_SCC_PCLK 10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MVME162_IRQ_TYPE_PRIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MVME167_IRQ_PRN (IRQ_USER+20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MVME16x_IRQ_I596 (IRQ_USER+23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MVME16x_IRQ_SCSI (IRQ_USER+21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MVME16x_IRQ_FLY (IRQ_USER+63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MVME167_IRQ_SER_ERR (IRQ_USER+28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MVME167_IRQ_SER_MODEM (IRQ_USER+29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MVME167_IRQ_SER_TX (IRQ_USER+30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MVME167_IRQ_SER_RX (IRQ_USER+31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MVME16x_IRQ_TIMER (IRQ_USER+25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MVME167_IRQ_ABORT (IRQ_USER+46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MVME162_IRQ_ABORT (IRQ_USER+30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* SCC interrupts, for MVME162 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MVME162_IRQ_SCC_BASE (IRQ_USER+0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MVME162_IRQ_SCCB_TX (IRQ_USER+0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MVME162_IRQ_SCCB_STAT (IRQ_USER+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MVME162_IRQ_SCCB_RX (IRQ_USER+4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MVME162_IRQ_SCCB_SPCOND (IRQ_USER+6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MVME162_IRQ_SCCA_TX (IRQ_USER+8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MVME162_IRQ_SCCA_STAT (IRQ_USER+10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MVME162_IRQ_SCCA_RX (IRQ_USER+12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MVME162_IRQ_SCCA_SPCOND (IRQ_USER+14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* MVME162 version register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MVME162_VERSION_REG 0xfff4202e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern unsigned short mvme16x_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Lower 8 bits must match the revision register in the MC2 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MVME16x_CONFIG_SPEED_32 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MVME16x_CONFIG_NO_VMECHIP2 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MVME16x_CONFIG_NO_SCSICHIP 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MVME16x_CONFIG_NO_ETHERNET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MVME16x_CONFIG_GOT_FPU 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MVME16x_CONFIG_GOT_LP 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MVME16x_CONFIG_GOT_CD2401 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MVME16x_CONFIG_GOT_SCCA 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MVME16x_CONFIG_GOT_SCCB 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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