^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _MVME147HW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _MVME147HW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) unsigned char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) bcd_sec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) bcd_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) bcd_hr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) bcd_dow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) bcd_dom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) bcd_mth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) bcd_year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) } MK48T02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RTC_WRITE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RTC_READ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RTC_STOP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define m147_rtc ((MK48T02 * volatile)0xfffe07f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct pcc_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) volatile u_long dma_tadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) volatile u_long dma_dadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) volatile u_long dma_bcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) volatile u_long dma_hr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) volatile u_short t1_preload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) volatile u_short t1_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) volatile u_short t2_preload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) volatile u_short t2_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) volatile u_char t1_int_cntrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) volatile u_char t1_cntrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) volatile u_char t2_int_cntrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) volatile u_char t2_cntrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) volatile u_char ac_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) volatile u_char watchdog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) volatile u_char lpt_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) volatile u_char lpt_cntrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) volatile u_char dma_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) volatile u_char dma_cntrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) volatile u_char bus_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) volatile u_char dma_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) volatile u_char abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) volatile u_char ta_fnctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) volatile u_char serial_cntrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) volatile u_char general_cntrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) volatile u_char lan_cntrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) volatile u_char general_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) volatile u_char scsi_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) volatile u_char slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) volatile u_char soft1_cntrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) volatile u_char int_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) volatile u_char soft2_cntrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) volatile u_char revision_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) volatile u_char lpt_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) volatile u_char lpt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define m147_pcc ((struct pcc_regs * volatile)0xfffe1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCC_INT_ENAB 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCC_TIMER_INT_CLR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCC_TIMER_TIC_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCC_TIMER_COC_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCC_TIMER_CLR_OVF 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCC_LEVEL_ABORT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCC_LEVEL_SERIAL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCC_LEVEL_ETH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCC_LEVEL_TIMER1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCC_LEVEL_SCSI_PORT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCC_LEVEL_SCSI_DMA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCC_IRQ_AC_FAIL (IRQ_USER+0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PCC_IRQ_BERR (IRQ_USER+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCC_IRQ_ABORT (IRQ_USER+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* #define PCC_IRQ_SERIAL (IRQ_USER+3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCC_IRQ_PRINTER (IRQ_USER+7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCC_IRQ_TIMER1 (IRQ_USER+8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCC_IRQ_TIMER2 (IRQ_USER+9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCC_IRQ_SOFTWARE1 (IRQ_USER+10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCC_IRQ_SOFTWARE2 (IRQ_USER+11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define M147_SCC_A_ADDR 0xfffe3002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define M147_SCC_B_ADDR 0xfffe3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define M147_SCC_PCLK 5000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MVME147_IRQ_SCSI_PORT (IRQ_USER+0x45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MVME147_IRQ_SCSI_DMA (IRQ_USER+0x46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* SCC interrupts, for MVME147 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MVME147_IRQ_TYPE_PRIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MVME147_IRQ_SCC_BASE (IRQ_USER+32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MVME147_IRQ_SCCB_TX (IRQ_USER+32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MVME147_IRQ_SCCB_STAT (IRQ_USER+34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MVME147_IRQ_SCCB_RX (IRQ_USER+36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MVME147_IRQ_SCCB_SPCOND (IRQ_USER+38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MVME147_IRQ_SCCA_TX (IRQ_USER+40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MVME147_IRQ_SCCA_STAT (IRQ_USER+42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MVME147_IRQ_SCCA_RX (IRQ_USER+44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MVME147_IRQ_SCCA_SPCOND (IRQ_USER+46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MVME147_LANCE_BASE 0xfffe1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MVME147_LANCE_IRQ (IRQ_USER+4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ETHERNET_ADDRESS 0xfffe0778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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