^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * mcfdebug.h -- ColdFire Debug Module support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 2001, Lineo Inc. (www.lineo.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef mcfdebug_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define mcfdebug_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Define the debug module registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MCFDEBUG_CSR 0x0 /* Configuration status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MCFDEBUG_BAAR 0x5 /* BDM address attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MCFDEBUG_AATR 0x6 /* Address attribute trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MCFDEBUG_TDR 0x7 /* Trigger definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MCFDEBUG_PBR 0x8 /* PC breakpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MCFDEBUG_PBMR 0x9 /* PC breakpoint mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MCFDEBUG_ABHR 0xc /* High address breakpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MCFDEBUG_ABLR 0xd /* Low address breakpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MCFDEBUG_DBR 0xe /* Data breakpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MCFDEBUG_DBMR 0xf /* Data breakpoint mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Define some handy constants for the trigger definition register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MCFDEBUG_TDR_TRC_DISP 0x00000000 /* display on DDATA only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MCFDEBUG_TDR_TRC_HALT 0x40000000 /* Processor halt on BP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MCFDEBUG_TDR_TRC_INTR 0x80000000 /* Debug intr on BP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MCFDEBUG_TDR_LXT1 0x00004000 /* TDR level 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCFDEBUG_TDR_LXT2 0x00008000 /* TDR level 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCFDEBUG_TDR_EBL1 0x00002000 /* Enable breakpoint level 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCFDEBUG_TDR_EBL2 0x20000000 /* Enable breakpoint level 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCFDEBUG_TDR_EDLW1 0x00001000 /* Enable data BP longword */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCFDEBUG_TDR_EDLW2 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCFDEBUG_TDR_EDWL1 0x00000800 /* Enable data BP lower word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MCFDEBUG_TDR_EDWL2 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MCFDEBUG_TDR_EDWU1 0x00000400 /* Enable data BP upper word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MCFDEBUG_TDR_EDWU2 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCFDEBUG_TDR_EDLL1 0x00000200 /* Enable data BP low low byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCFDEBUG_TDR_EDLL2 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MCFDEBUG_TDR_EDLM1 0x00000100 /* Enable data BP low mid byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MCFDEBUG_TDR_EDLM2 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MCFDEBUG_TDR_EDUM1 0x00000080 /* Enable data BP up mid byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MCFDEBUG_TDR_EDUM2 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCFDEBUG_TDR_EDUU1 0x00000040 /* Enable data BP up up byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MCFDEBUG_TDR_EDUU2 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MCFDEBUG_TDR_DI1 0x00000020 /* Data BP invert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MCFDEBUG_TDR_DI2 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MCFDEBUG_TDR_EAI1 0x00000010 /* Enable address BP inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MCFDEBUG_TDR_EAI2 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MCFDEBUG_TDR_EAR1 0x00000008 /* Enable address BP range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MCFDEBUG_TDR_EAR2 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MCFDEBUG_TDR_EAL1 0x00000004 /* Enable address BP low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MCFDEBUG_TDR_EAL2 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MCFDEBUG_TDR_EPC1 0x00000002 /* Enable PC BP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MCFDEBUG_TDR_EPC2 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MCFDEBUG_TDR_PCI1 0x00000001 /* PC BP invert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MCFDEBUG_TDR_PCI2 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Constants for the address attribute trigger register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MCFDEBUG_AAR_RESET 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Fields not yet implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* And some definitions for the writable sections of the CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MCFDEBUG_CSR_RESET 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MCFDEBUG_CSR_PSTCLK 0x00020000 /* PSTCLK disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MCFDEBUG_CSR_IPW 0x00010000 /* Inhibit processor writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MCFDEBUG_CSR_MAP 0x00008000 /* Processor refs in emul mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MCFDEBUG_CSR_TRC 0x00004000 /* Emul mode on trace exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MCFDEBUG_CSR_EMU 0x00002000 /* Force emulation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MCFDEBUG_CSR_DDC_READ 0x00000800 /* Debug data control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MCFDEBUG_CSR_DDC_WRITE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MCFDEBUG_CSR_UHE 0x00000400 /* User mode halt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MCFDEBUG_CSR_BTB0 0x00000000 /* Branch target 0 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MCFDEBUG_CSR_BTB2 0x00000100 /* Branch target 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MCFDEBUG_CSR_BTB3 0x00000200 /* Branch target 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MCFDEBUG_CSR_BTB4 0x00000300 /* Branch target 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MCFDEBUG_CSR_NPL 0x00000040 /* Non-pipelined mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MCFDEBUG_CSR_SSM 0x00000010 /* Single step mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Constants for the BDM address attribute register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MCFDEBUG_BAAR_RESET 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Fields not yet implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* This routine wrappers up the wdebug asm instruction so that the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * and value can be relatively easily specified. The biggest hassle here is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * that the debug module instructions (2 longs) must be long word aligned and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * some pointer fiddling is performed to ensure this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline void wdebug(int reg, unsigned long data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned short dbg_spc[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned short *dbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) // Force alignment to long word boundary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dbg = (unsigned short *)((((unsigned long)dbg_spc) + 3) & 0xfffffffc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) // Build up the debug instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dbg[0] = 0x2c80 | (reg & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dbg[1] = (data >> 16) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dbg[2] = data & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dbg[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) // Perform the wdebug instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) // This strain is for gas which doesn't have the wdebug instructions defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) asm( "move.l %0, %%a0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ".word 0xfbd0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ".word 0x0003\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) :: "g" (dbg) : "a0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) // And this is for when it does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) asm( "wdebug (%0)" :: "a" (dbg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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