Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	mcfuart.h -- ColdFire internal UART support defines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	(C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * 	(C) Copyright 2000, Lineo Inc. (www.lineo.com) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #ifndef	mcfuart_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define	mcfuart_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) struct mcf_platform_uart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	unsigned long	mapbase;	/* Physical address base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	void __iomem	*membase;	/* Virtual address if mapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	unsigned int	irq;		/* Interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	unsigned int	uartclk;	/* UART clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *	Define the ColdFire UART register set addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define	MCFUART_UMR		0x00		/* Mode register (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define	MCFUART_USR		0x04		/* Status register (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define	MCFUART_UCSR		0x04		/* Clock Select (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define	MCFUART_UCR		0x08		/* Command register (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define	MCFUART_URB		0x0c		/* Receiver Buffer (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define	MCFUART_UTB		0x0c		/* Transmit Buffer (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define	MCFUART_UIPCR		0x10		/* Input Port Change (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define	MCFUART_UACR		0x10		/* Auxiliary Control (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define	MCFUART_UISR		0x14		/* Interrupt Status (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define	MCFUART_UIMR		0x14		/* Interrupt Mask (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	MCFUART_UBG1		0x18		/* Baud Rate MSB (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define	MCFUART_UBG2		0x1c		/* Baud Rate LSB (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #ifdef	CONFIG_M5272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define	MCFUART_UTF		0x28		/* Transmitter FIFO (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define	MCFUART_URF		0x2c		/* Receiver FIFO (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define	MCFUART_UFPD		0x30		/* Frac Prec. Divider (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	defined(CONFIG_M5307) || defined(CONFIG_M5407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define	MCFUART_UIVR		0x30		/* Interrupt Vector (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define	MCFUART_UIPR		0x34		/* Input Port (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define	MCFUART_UOP1		0x38		/* Output Port Bit Set (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define	MCFUART_UOP0		0x3c		/* Output Port Bit Reset (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  *	Define bit flags in Mode Register 1 (MR1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define	MCFUART_MR1_RXRTS	0x80		/* Auto RTS flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define	MCFUART_MR1_RXIRQFULL	0x40		/* RX IRQ type FULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define	MCFUART_MR1_RXIRQRDY	0x00		/* RX IRQ type RDY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define	MCFUART_MR1_RXERRBLOCK	0x20		/* RX block error mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define	MCFUART_MR1_RXERRCHAR	0x00		/* RX char error mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define	MCFUART_MR1_PARITYNONE	0x10		/* No parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define	MCFUART_MR1_PARITYEVEN	0x00		/* Even parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define	MCFUART_MR1_PARITYODD	0x04		/* Odd parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define	MCFUART_MR1_PARITYSPACE	0x08		/* Space parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define	MCFUART_MR1_PARITYMARK	0x0c		/* Mark parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define	MCFUART_MR1_CS5		0x00		/* 5 bits per char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define	MCFUART_MR1_CS6		0x01		/* 6 bits per char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define	MCFUART_MR1_CS7		0x02		/* 7 bits per char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define	MCFUART_MR1_CS8		0x03		/* 8 bits per char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  *	Define bit flags in Mode Register 2 (MR2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define	MCFUART_MR2_LOOPBACK	0x80		/* Loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define	MCFUART_MR2_REMOTELOOP	0xc0		/* Remote loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define	MCFUART_MR2_AUTOECHO	0x40		/* Automatic echo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define	MCFUART_MR2_TXRTS	0x20		/* Assert RTS on TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define	MCFUART_MR2_TXCTS	0x10		/* Auto CTS flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define	MCFUART_MR2_STOP1	0x07		/* 1 stop bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define	MCFUART_MR2_STOP15	0x08		/* 1.5 stop bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define	MCFUART_MR2_STOP2	0x0f		/* 2 stop bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  *	Define bit flags in Status Register (USR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define	MCFUART_USR_RXBREAK	0x80		/* Received BREAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define	MCFUART_USR_RXFRAMING	0x40		/* Received framing error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define	MCFUART_USR_RXPARITY	0x20		/* Received parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define	MCFUART_USR_RXOVERRUN	0x10		/* Received overrun error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define	MCFUART_USR_TXEMPTY	0x08		/* Transmitter empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define	MCFUART_USR_TXREADY	0x04		/* Transmitter ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define	MCFUART_USR_RXFULL	0x02		/* Receiver full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define	MCFUART_USR_RXREADY	0x01		/* Receiver ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define	MCFUART_USR_RXERR	(MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 				MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  *	Define bit flags in Clock Select Register (UCSR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define	MCFUART_UCSR_RXCLKTIMER	0xd0		/* RX clock is timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define	MCFUART_UCSR_RXCLKEXT16	0xe0		/* RX clock is external x16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define	MCFUART_UCSR_RXCLKEXT1	0xf0		/* RX clock is external x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define	MCFUART_UCSR_TXCLKTIMER	0x0d		/* TX clock is timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define	MCFUART_UCSR_TXCLKEXT16	0x0e		/* TX clock is external x16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define	MCFUART_UCSR_TXCLKEXT1	0x0f		/* TX clock is external x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  *	Define bit flags in Command Register (UCR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define	MCFUART_UCR_CMDNULL		0x00	/* No command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define	MCFUART_UCR_CMDRESETMRPTR	0x10	/* Reset MR pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define	MCFUART_UCR_CMDRESETRX		0x20	/* Reset receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define	MCFUART_UCR_CMDRESETTX		0x30	/* Reset transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define	MCFUART_UCR_CMDRESETERR		0x40	/* Reset error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define	MCFUART_UCR_CMDRESETBREAK	0x50	/* Reset BREAK change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define	MCFUART_UCR_CMDBREAKSTART	0x60	/* Start BREAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define	MCFUART_UCR_CMDBREAKSTOP	0x70	/* Stop BREAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define	MCFUART_UCR_TXNULL	0x00		/* No TX command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define	MCFUART_UCR_TXENABLE	0x04		/* Enable TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define	MCFUART_UCR_TXDISABLE	0x08		/* Disable TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define	MCFUART_UCR_RXNULL	0x00		/* No RX command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define	MCFUART_UCR_RXENABLE	0x01		/* Enable RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define	MCFUART_UCR_RXDISABLE	0x02		/* Disable RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  *	Define bit flags in Input Port Change Register (UIPCR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define	MCFUART_UIPCR_CTSCOS	0x10		/* CTS change of state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define	MCFUART_UIPCR_CTS	0x01		/* CTS value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  *	Define bit flags in Input Port Register (UIP).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define	MCFUART_UIPR_CTS	0x01		/* CTS value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  *	Define bit flags in Output Port Registers (UOP).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  *	Clear bit by writing to UOP0, set by writing to UOP1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define	MCFUART_UOP_RTS		0x01		/* RTS set or clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  *	Define bit flags in the Auxiliary Control Register (UACR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define	MCFUART_UACR_IEC	0x01		/* Input enable control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  *	Define bit flags in Interrupt Status Register (UISR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  *	These same bits are used for the Interrupt Mask Register (UIMR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define	MCFUART_UIR_COS		0x80		/* Change of state (CTS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define	MCFUART_UIR_DELTABREAK	0x04		/* Break start or stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define	MCFUART_UIR_RXREADY	0x02		/* Receiver ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define	MCFUART_UIR_TXREADY	0x01		/* Transmitter ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef	CONFIG_M5272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  *	Define bit flags in the Transmitter FIFO Register (UTF).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define	MCFUART_UTF_TXB		0x1f		/* Transmitter data level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define	MCFUART_UTF_FULL	0x20		/* Transmitter fifo full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define	MCFUART_UTF_TXS		0xc0		/* Transmitter status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  *	Define bit flags in the Receiver FIFO Register (URF).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define	MCFUART_URF_RXB		0x1f		/* Receiver data level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define	MCFUART_URF_FULL	0x20		/* Receiver fifo full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define	MCFUART_URF_RXS		0xc0		/* Receiver status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #if defined(CONFIG_M54xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MCFUART_TXFIFOSIZE	512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #elif defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MCFUART_TXFIFOSIZE	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MCFUART_TXFIFOSIZE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif	/* mcfuart_h */