Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	mcftimer.h -- ColdFire internal TIMER support defines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	(C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * 	(C) Copyright 2000, Lineo Inc. (www.lineo.com) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef	mcftimer_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define	mcftimer_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  *	Define the TIMER register set addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define	MCFTIMER_TMR		0x00		/* Timer Mode reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define	MCFTIMER_TRR		0x04		/* Timer Reference (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define	MCFTIMER_TCR		0x08		/* Timer Capture reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define	MCFTIMER_TCN		0x0C		/* Timer Counter reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define	MCFTIMER_TER		0x03		/* Timer Event reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define	MCFTIMER_TER		0x11		/* Timer Event reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  *	Bit definitions for the Timer Mode Register (TMR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  *	Register bit flags are common across ColdFires.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define	MCFTIMER_TMR_PREMASK	0xff00		/* Prescalar mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define	MCFTIMER_TMR_DISCE	0x0000		/* Disable capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define	MCFTIMER_TMR_ANYCE	0x00c0		/* Capture any edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define	MCFTIMER_TMR_FALLCE	0x0080		/* Capture fallingedge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define	MCFTIMER_TMR_RISECE	0x0040		/* Capture rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define	MCFTIMER_TMR_ENOM	0x0020		/* Enable output toggle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define	MCFTIMER_TMR_DISOM	0x0000		/* Do single output pulse  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define	MCFTIMER_TMR_ENORI	0x0010		/* Enable ref interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define	MCFTIMER_TMR_DISORI	0x0000		/* Disable ref interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define	MCFTIMER_TMR_RESTART	0x0008		/* Restart counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define	MCFTIMER_TMR_FREERUN	0x0000		/* Free running counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define	MCFTIMER_TMR_CLKTIN	0x0006		/* Input clock is TIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define	MCFTIMER_TMR_CLK16	0x0004		/* Input clock is /16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define	MCFTIMER_TMR_CLK1	0x0002		/* Input clock is /1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define	MCFTIMER_TMR_CLKSTOP	0x0000		/* Stop counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define	MCFTIMER_TMR_ENABLE	0x0001		/* Enable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define	MCFTIMER_TMR_DISABLE	0x0000		/* Disable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)  *	Bit definitions for the Timer Event Registers (TER).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define	MCFTIMER_TER_CAP	0x01		/* Capture event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define	MCFTIMER_TER_REF	0x02		/* Reference event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif	/* mcftimer_h */