Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	mcfslt.h -- ColdFire internal Slice (SLT) timer support defines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	(C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *	(C) Copyright 2009, Philippe De Muyter (phdm@macqel.be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef mcfslt_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define mcfslt_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  *	Define the SLT timer register set addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MCFSLT_STCNT		0x00	/* Terminal count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MCFSLT_SCR		0x04	/* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MCFSLT_SCNT		0x08	/* Current count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MCFSLT_SSR		0x0C	/* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  *	Bit definitions for the SCR control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MCFSLT_SCR_RUN		0x04000000	/* Run mode (continuous) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MCFSLT_SCR_IEN		0x02000000	/* Interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MCFSLT_SCR_TEN		0x01000000	/* Timer enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  *	Bit definitions for the SSR status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCFSLT_SSR_BE		0x02000000	/* Bus error condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCFSLT_SSR_TE		0x01000000	/* Timeout condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif	/* mcfslt_h */