Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	mcfpit.h -- ColdFire internal PIT timer support defines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	(C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef	mcfpit_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define	mcfpit_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  *	Define the PIT timer register address offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define	MCFPIT_PCSR		0x0		/* PIT control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define	MCFPIT_PMR		0x2		/* PIT modulus register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define	MCFPIT_PCNTR		0x4		/* PIT count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  *	Bit definitions for the PIT Control and Status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define	MCFPIT_PCSR_CLK1	0x0000		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define	MCFPIT_PCSR_CLK2	0x0100		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define	MCFPIT_PCSR_CLK4	0x0200		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define	MCFPIT_PCSR_CLK8	0x0300		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define	MCFPIT_PCSR_CLK16	0x0400		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define	MCFPIT_PCSR_CLK32	0x0500		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define	MCFPIT_PCSR_CLK64	0x0600		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define	MCFPIT_PCSR_CLK128	0x0700		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define	MCFPIT_PCSR_CLK256	0x0800		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define	MCFPIT_PCSR_CLK512	0x0900		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define	MCFPIT_PCSR_CLK1024	0x0a00		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define	MCFPIT_PCSR_CLK2048	0x0b00		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define	MCFPIT_PCSR_CLK4096	0x0c00		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define	MCFPIT_PCSR_CLK8192	0x0d00		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define	MCFPIT_PCSR_CLK16384	0x0e00		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define	MCFPIT_PCSR_CLK32768	0x0f00		/* System clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define	MCFPIT_PCSR_DOZE	0x0040		/* Clock run in doze mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define	MCFPIT_PCSR_HALTED	0x0020		/* Clock run in halt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define	MCFPIT_PCSR_OVW		0x0010		/* Overwrite PIT counter now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define	MCFPIT_PCSR_PIE		0x0008		/* Enable PIT interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define	MCFPIT_PCSR_PIF		0x0004		/* PIT interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define	MCFPIT_PCSR_RLD		0x0002		/* Reload counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define	MCFPIT_PCSR_EN		0x0001		/* Enable PIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define	MCFPIT_PCSR_DISABLE	0x0000		/* Disable PIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif	/* mcfpit_h */