^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * mcfmmu.h -- definitions for the ColdFire v4e MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef MCFMMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MCFMMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The MMU support registers are mapped into the address space using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * the processor MMUBASE register. We used a fixed address for mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * there doesn't seem any need to make this configurable yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MMUBASE 0xfe000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * The support registers of the MMU. Names are the sames as those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * used in the Freescale v4e documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MMUCR (MMUBASE + 0x00) /* Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MMUOR (MMUBASE + 0x04) /* Operation register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MMUSR (MMUBASE + 0x08) /* Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MMUAR (MMUBASE + 0x10) /* TLB Address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MMUTR (MMUBASE + 0x14) /* TLB Tag register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MMUDR (MMUBASE + 0x18) /* TLB Data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * MMU Control register bit flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MMUCR_EN 0x00000001 /* Virtual mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MMUCR_ASM 0x00000002 /* Address space mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * MMU Operation register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MMUOR_UAA 0x00000001 /* Update allocation address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MMUOR_ACC 0x00000002 /* TLB access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MMUOR_RD 0x00000004 /* TLB access read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MMUOR_WR 0x00000000 /* TLB access write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MMUOR_ADR 0x00000008 /* TLB address select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MMUOR_ITLB 0x00000010 /* ITLB operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MMUOR_CA 0x00000080 /* Clear all TLBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MMUOR_STLB 0x00000100 /* Search TLBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MMUOR_AAN 16 /* TLB allocation address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MMUOR_AAMASK 0xffff0000 /* AA mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * MMU Status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MMUSR_HIT 0x00000002 /* Search TLB hit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MMUSR_WF 0x00000008 /* Write access fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MMUSR_RF 0x00000010 /* Read access fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MMUSR_SPF 0x00000020 /* Supervisor protect fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * MMU Read/Write Tag register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MMUTR_V 0x00000001 /* Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MMUTR_SG 0x00000002 /* Shared global */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MMUTR_IDN 2 /* Address Space ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MMUTR_IDMASK 0x000003fc /* ASID mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MMUTR_VAN 10 /* Virtual Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MMUTR_VAMASK 0xfffffc00 /* VA mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * MMU Read/Write Data register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MMUDR_LK 0x00000002 /* Lock entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MMUDR_X 0x00000004 /* Execute access enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MMUDR_W 0x00000008 /* Write access enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MMUDR_R 0x00000010 /* Read access enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MMUDR_SP 0x00000020 /* Supervisor access enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MMUDR_CM_CWT 0x00000000 /* Cachable write thru */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MMUDR_CM_CCB 0x00000040 /* Cachable copy back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MMUDR_CM_NCP 0x00000080 /* Non-cachable precise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MMUDR_CM_NCI 0x000000c0 /* Non-cachable imprecise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MMUDR_SZ_1MB 0x00000000 /* 1MB page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MMUDR_SZ_4KB 0x00000100 /* 4kB page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MMUDR_SZ_8KB 0x00000200 /* 8kB page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MMUDR_SZ_1KB 0x00000300 /* 1kB page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MMUDR_PAN 10 /* Physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MMUDR_PAMASK 0xfffffc00 /* PA mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Simple access functions for the MMU registers. Nothing fancy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * currently required, just simple 32bit access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline u32 mmu_read(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return *((volatile u32 *) a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline void mmu_write(u32 a, u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *((volatile u32 *) a) = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __asm__ __volatile__ ("nop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void cf_bootmem_alloc(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void cf_mmu_context_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif /* MCFMMU_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags