^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * mcfintc.h -- support definitions for the simple ColdFire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Interrupt Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright 2009, Greg Ungerer <gerg@uclinux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef mcfintc_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define mcfintc_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Most of the older ColdFire parts use the same simple interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * controller. This is currently used on the 5206, 5206e, 5249, 5307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * and 5407 parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * The builtin peripherals are masked through dedicated bits in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Interrupt Mask register (IMR) - and this is not indexed (or in any way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * related to) the actual interrupt number they use. So knowing the IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * number doesn't explicitly map to a certain internal device for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * interrupt control purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Bit definitions for the ICR family of registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * IMR bit position definitions. Not all ColdFire parts with this interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * controller actually support all of these interrupt sources. But the bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * numbers are the same in all cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MCFINTC_EINT1 1 /* External int #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MCFINTC_EINT2 2 /* External int #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MCFINTC_EINT3 3 /* External int #3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MCFINTC_EINT4 4 /* External int #4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MCFINTC_EINT5 5 /* External int #5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MCFINTC_EINT6 6 /* External int #6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MCFINTC_EINT7 7 /* External int #7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MCFINTC_SWT 8 /* Software Watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MCFINTC_TIMER1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MCFINTC_TIMER2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MCFINTC_I2C 11 /* I2C / MBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MCFINTC_UART0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MCFINTC_UART1 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MCFINTC_DMA0 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MCFINTC_DMA1 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MCFINTC_DMA2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MCFINTC_DMA3 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MCFINTC_QSPI 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * There is no one-is-one correspondance between the interrupt number (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * and the bit fields on the mask register. So we create a per-cpu type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * mapping of irq to mask bit. The CPU platform code needs to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * its supported irq's at init time, using this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) extern unsigned char mcf_irq2imr[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline void mcf_mapirq2imr(int irq, int imr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mcf_irq2imr[irq] = imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void mcf_autovector(int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void mcf_setimr(int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void mcf_clrimr(int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif /* mcfintc_h */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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