Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Coldfire generic GPIO support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef mcfgpio_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define mcfgpio_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm-generic/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) int __mcfgpio_get_value(unsigned gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) void __mcfgpio_set_value(unsigned gpio, int value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) int __mcfgpio_direction_input(unsigned gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) int __mcfgpio_direction_output(unsigned gpio, int value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) int __mcfgpio_request(unsigned gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) void __mcfgpio_free(unsigned gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* our alternate 'gpiolib' functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static inline int __gpio_get_value(unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	if (gpio < MCFGPIO_PIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		return __mcfgpio_get_value(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static inline void __gpio_set_value(unsigned gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	if (gpio < MCFGPIO_PIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		__mcfgpio_set_value(gpio, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static inline int __gpio_cansleep(unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	if (gpio < MCFGPIO_PIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static inline int __gpio_to_irq(unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static inline int gpio_direction_input(unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	if (gpio < MCFGPIO_PIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		return __mcfgpio_direction_input(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static inline int gpio_direction_output(unsigned gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (gpio < MCFGPIO_PIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		return __mcfgpio_direction_output(gpio, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static inline int gpio_request(unsigned gpio, const char *label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (gpio < MCFGPIO_PIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		return __mcfgpio_request(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static inline void gpio_free(unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	if (gpio < MCFGPIO_PIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		__mcfgpio_free(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #endif /* CONFIG_GPIOLIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * The Freescale Coldfire family is quite varied in how they implement GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * only one port, others have multiple ports; some have a single data latch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * for both input and output, others have a separate pin data register to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * input; some require a read-modify-write access to change an output, others
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * have set and clear registers for some of the outputs; Some have all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * GPIOs in a single control area, others have some GPIOs implemented in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * different modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * This implementation attempts accommodate the differences while presenting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * a generic interface that will optimize to as few instructions as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)     defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)     defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)     defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)     defined(CONFIG_M5441x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* These parts have GPIO organized by 8 bit ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MCFGPIO_PORTTYPE		u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MCFGPIO_PORTSIZE		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define mcfgpio_read(port)		__raw_readb(port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define mcfgpio_write(data, port)	__raw_writeb(data, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* These parts have GPIO organized by 16 bit ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MCFGPIO_PORTTYPE		u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCFGPIO_PORTSIZE		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define mcfgpio_read(port)		__raw_readw(port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define mcfgpio_write(data, port)	__raw_writew(data, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* These parts have GPIO organized by 32 bit ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MCFGPIO_PORTTYPE		u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MCFGPIO_PORTSIZE		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define mcfgpio_read(port)		__raw_readl(port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define mcfgpio_write(data, port)	__raw_writel(data, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define mcfgpio_bit(gpio)		(1 << ((gpio) %  MCFGPIO_PORTSIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define mcfgpio_port(gpio)		((gpio) / MCFGPIO_PORTSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)     defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)     defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)     defined(CONFIG_M5441x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  * read-modify-write to change an output and a GPIO module which has separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * set/clr registers to directly change outputs with a single write access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #if defined(CONFIG_M528x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * The 528x also has GPIOs in other modules (GPT, QADC) which use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * read-modify-write as well as those controlled by the EPORT and GPIO modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MCFGPIO_SCR_START		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #elif defined(CONFIGM5441x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MCFGPIO_SCR_START		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MCFGPIO_SCR_START		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MCFGPIO_SETR_PORT(gpio)		(MCFGPIO_SETR + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 					mcfgpio_port(gpio - MCFGPIO_SCR_START))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MCFGPIO_CLRR_PORT(gpio)		(MCFGPIO_CLRR + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 					mcfgpio_port(gpio - MCFGPIO_SCR_START))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MCFGPIO_SCR_START		MCFGPIO_PIN_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MCFGPIO_SETR_PORT(gpio)		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MCFGPIO_CLRR_PORT(gpio)		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * Coldfire specific helper functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* return the port pin data register for a gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline u32 __mcfgpio_ppdr(unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)     defined(CONFIG_M5307) || defined(CONFIG_M5407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return MCFSIM_PADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #elif defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (gpio < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return MCFSIM_PADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	else if (gpio < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return MCFSIM_PBDAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return MCFSIM_PCDAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (gpio < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return MCFSIM2_GPIOREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return MCFSIM2_GPIO1READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)       defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)       defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)       defined(CONFIG_M5441x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #if !defined(CONFIG_M5441x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (gpio < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return MCFEPORT_EPPDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #if defined(CONFIG_M528x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	else if (gpio < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return MCFGPTA_GPTPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	else if (gpio < 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return MCFGPTB_GPTPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	else if (gpio < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return MCFQADC_PORTQA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	else if (gpio < 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return MCFQADC_PORTQB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #endif /* defined(CONFIG_M528x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif /* !defined(CONFIG_M5441x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* return the port output data register for a gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static inline u32 __mcfgpio_podr(unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)     defined(CONFIG_M5307) || defined(CONFIG_M5407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	return MCFSIM_PADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #elif defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (gpio < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return MCFSIM_PADAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	else if (gpio < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return MCFSIM_PBDAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return MCFSIM_PCDAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (gpio < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return MCFSIM2_GPIOWRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return MCFSIM2_GPIO1WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)       defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)       defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)       defined(CONFIG_M5441x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #if !defined(CONFIG_M5441x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (gpio < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return MCFEPORT_EPDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #if defined(CONFIG_M528x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	else if (gpio < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return MCFGPTA_GPTPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	else if (gpio < 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		return MCFGPTB_GPTPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	else if (gpio < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return MCFQADC_PORTQA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	else if (gpio < 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return MCFQADC_PORTQB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #endif /* defined(CONFIG_M528x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #endif /* !defined(CONFIG_M5441x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* return the port direction data register for a gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static inline u32 __mcfgpio_pddr(unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)     defined(CONFIG_M5307) || defined(CONFIG_M5407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return MCFSIM_PADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #elif defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (gpio < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return MCFSIM_PADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	else if (gpio < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return MCFSIM_PBDDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return MCFSIM_PCDDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (gpio < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return MCFSIM2_GPIOENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return MCFSIM2_GPIO1ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)       defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)       defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)       defined(CONFIG_M5441x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #if !defined(CONFIG_M5441x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (gpio < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		return MCFEPORT_EPDDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #if defined(CONFIG_M528x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	else if (gpio < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return MCFGPTA_GPTDDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	else if (gpio < 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return MCFGPTB_GPTDDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	else if (gpio < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return MCFQADC_DDRQA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	else if (gpio < 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return MCFQADC_DDRQB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #endif /* defined(CONFIG_M528x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif /* !defined(CONFIG_M5441x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #endif /* mcfgpio_h */