^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * mcfdma.h -- Coldfire internal DMA support defines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 1999, Rob Scott (rscott@mtrob.ml.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef mcfdma_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define mcfdma_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #if !defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Define the DMA register set addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Note: these are longword registers, use unsigned long as data type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MCFDMA_SAR 0x00 /* DMA source address (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MCFDMA_DAR 0x01 /* DMA destination adr (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* these are word registers, use unsigned short data type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MCFDMA_DCR 0x04 /* DMA control reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MCFDMA_BCR 0x06 /* DMA byte count reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* these are byte registers, use unsiged char data type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MCFDMA_DSR 0x10 /* DMA status reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Bit definitions for the DMA Control Register (DCR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCFDMA_DCR_INT 0x8000 /* Enable completion irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCFDMA_DCR_EEXT 0x4000 /* Enable external DMA req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCFDMA_DCR_CS 0x2000 /* Enable cycle steal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCFDMA_DCR_AA 0x1000 /* Enable auto alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCFDMA_DCR_BWC_MASK 0x0E00 /* Bandwidth ctl mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MCFDMA_DCR_BWC_512 0x0200 /* Bandwidth: 512 Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MCFDMA_DCR_BWC_1024 0x0400 /* Bandwidth: 1024 Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MCFDMA_DCR_BWC_2048 0x0600 /* Bandwidth: 2048 Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCFDMA_DCR_BWC_4096 0x0800 /* Bandwidth: 4096 Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCFDMA_DCR_BWC_8192 0x0a00 /* Bandwidth: 8192 Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MCFDMA_DCR_BWC_16384 0x0c00 /* Bandwidth: 16384 Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MCFDMA_DCR_BWC_32768 0x0e00 /* Bandwidth: 32768 Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MCFDMA_DCR_SAA 0x0100 /* Single Address Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MCFDMA_DCR_S_RW 0x0080 /* SAA read/write value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCFDMA_DCR_SINC 0x0040 /* Source addr inc enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MCFDMA_DCR_SSIZE_MASK 0x0030 /* Src xfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MCFDMA_DCR_SSIZE_LONG 0x0000 /* Src xfer size, 00 = longw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MCFDMA_DCR_SSIZE_BYTE 0x0010 /* Src xfer size, 01 = byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MCFDMA_DCR_SSIZE_WORD 0x0020 /* Src xfer size, 10 = word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MCFDMA_DCR_SSIZE_LINE 0x0030 /* Src xfer size, 11 = line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MCFDMA_DCR_DINC 0x0008 /* Dest addr inc enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MCFDMA_DCR_DSIZE_MASK 0x0006 /* Dest xfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MCFDMA_DCR_DSIZE_LONG 0x0000 /* Dest xfer size, 00 = long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MCFDMA_DCR_DSIZE_BYTE 0x0002 /* Dest xfer size, 01 = byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MCFDMA_DCR_DSIZE_WORD 0x0004 /* Dest xfer size, 10 = word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MCFDMA_DCR_DSIZE_LINE 0x0006 /* Dest xfer size, 11 = line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MCFDMA_DCR_START 0x0001 /* Start transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Bit definitions for the DMA Status Register (DSR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MCFDMA_DSR_CE 0x40 /* Config error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MCFDMA_DSR_BES 0x20 /* Bus Error on source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MCFDMA_DSR_BED 0x10 /* Bus Error on dest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MCFDMA_DSR_REQ 0x04 /* Requests remaining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MCFDMA_DSR_BSY 0x02 /* Busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MCFDMA_DSR_DONE 0x01 /* DMA transfer complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #else /* This is an MCF5272 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MCFDMA_DMR 0x00 /* Mode Register (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MCFDMA_DIR 0x03 /* Interrupt trigger register (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MCFDMA_DSAR 0x03 /* Source Address register (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MCFDMA_DDAR 0x04 /* Destination Address register (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MCFDMA_DBCR 0x02 /* Byte Count Register (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Bit definitions for the DMA Mode Register (DMR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MCFDMA_DMR_RESET 0x80000000L /* Reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MCFDMA_DMR_EN 0x40000000L /* DMA enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MCFDMA_DMR_RQM 0x000C0000L /* Request Mode Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MCFDMA_DMR_RQM_DUAL 0x000C0000L /* Dual address mode, the only valid mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MCFDMA_DMR_DSTM 0x00002000L /* Destination addressing mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MCFDMA_DMR_DSTM_SA 0x00000000L /* Destination uses static addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MCFDMA_DMR_DSTM_IA 0x00002000L /* Destination uses incremental addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MCFDMA_DMR_DSTT_UD 0x00000400L /* Destination is user data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MCFDMA_DMR_DSTT_UC 0x00000800L /* Destination is user code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MCFDMA_DMR_DSTS_OFF 0x8 /* offset to the destination size bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MCFDMA_DMR_DSTS_LONG 0x00000000L /* Long destination size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MCFDMA_DMR_DSTS_BYTE 0x00000100L /* Byte destination size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MCFDMA_DMR_DSTS_WORD 0x00000200L /* Word destination size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MCFDMA_DMR_DSTS_LINE 0x00000300L /* Line destination size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MCFDMA_DMR_SRCM 0x00000020L /* Source addressing mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MCFDMA_DMR_SRCM_SA 0x00000000L /* Source uses static addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MCFDMA_DMR_SRCM_IA 0x00000020L /* Source uses incremental addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MCFDMA_DMR_SRCT_UD 0x00000004L /* Source is user data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MCFDMA_DMR_SRCT_UC 0x00000008L /* Source is user code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MCFDMA_DMR_SRCS_OFF 0x0 /* Offset to the source size bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MCFDMA_DMR_SRCS_LONG 0x00000000L /* Long source size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MCFDMA_DMR_SRCS_BYTE 0x00000001L /* Byte source size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MCFDMA_DMR_SRCS_WORD 0x00000002L /* Word source size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCFDMA_DMR_SRCS_LINE 0x00000003L /* Line source size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Bit definitions for the DMA interrupt register (DIR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MCFDMA_DIR_INVEN 0x1000 /* Invalid Combination interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MCFDMA_DIR_ASCEN 0x0800 /* Address Sequence Complete (Completion) interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MCFDMA_DIR_TEEN 0x0200 /* Transfer Error interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MCFDMA_DIR_TCEN 0x0100 /* Transfer Complete (a bus transfer, that is) interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCFDMA_DIR_INV 0x0010 /* Invalid Combination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MCFDMA_DIR_ASC 0x0008 /* Address Sequence Complete (DMA Completion) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MCFDMA_DIR_TE 0x0002 /* Transfer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MCFDMA_DIR_TC 0x0001 /* Transfer Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif /* !defined(CONFIG_M5272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif /* mcfdma_h */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags