^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ** macints.h -- Macintosh Linux interrupt handling structs and prototypes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) ** Copyright 1997 by Michael Schmitz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) ** This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) ** License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ** for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef _ASM_MACINTS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _ASM_MACINTS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Base IRQ number for all Mac68K interrupt sources. Each source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * has eight indexes (base -> base+7).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VIA1_SOURCE_BASE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VIA2_SOURCE_BASE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PSC3_SOURCE_BASE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PSC4_SOURCE_BASE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PSC5_SOURCE_BASE 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PSC6_SOURCE_BASE 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NUBUS_SOURCE_BASE 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BABOON_SOURCE_BASE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Maximum IRQ number is BABOON_SOURCE_BASE + 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * giving us IRQs up through 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NUM_MAC_SOURCES 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * clean way to separate IRQ into its source and index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IRQ_SRC(irq) (irq >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IRQ_IDX(irq) (irq & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* VIA1 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IRQ_VIA1_0 (8) /* one second int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IRQ_VIA1_1 (9) /* VBlank int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IRQ_MAC_VBL IRQ_VIA1_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IRQ_VIA1_2 (10) /* ADB SR shifts complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IRQ_MAC_ADB IRQ_VIA1_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IRQ_MAC_ADB_SR IRQ_VIA1_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IRQ_VIA1_3 (11) /* ADB SR CB2 ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IRQ_MAC_ADB_SD IRQ_VIA1_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IRQ_VIA1_4 (12) /* ADB SR ext. clock pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IRQ_MAC_ADB_CL IRQ_VIA1_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IRQ_VIA1_5 (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IRQ_MAC_TIMER_2 IRQ_VIA1_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IRQ_VIA1_6 (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IRQ_MAC_TIMER_1 IRQ_VIA1_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IRQ_VIA1_7 (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* VIA2/RBV interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IRQ_VIA2_0 (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IRQ_MAC_SCSIDRQ IRQ_VIA2_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IRQ_VIA2_1 (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IRQ_MAC_NUBUS IRQ_VIA2_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IRQ_VIA2_2 (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IRQ_VIA2_3 (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IRQ_MAC_SCSI IRQ_VIA2_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IRQ_VIA2_4 (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IRQ_VIA2_5 (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IRQ_VIA2_6 (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IRQ_VIA2_7 (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Level 3 (PSC, AV Macs only) interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IRQ_PSC3_0 (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IRQ_MAC_MACE IRQ_PSC3_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IRQ_PSC3_1 (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IRQ_PSC3_2 (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IRQ_PSC3_3 (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Level 4 (PSC, AV Macs only) interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IRQ_PSC4_0 (32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IRQ_PSC4_1 (33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IRQ_MAC_SCC_A IRQ_PSC4_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IRQ_PSC4_2 (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IRQ_MAC_SCC_B IRQ_PSC4_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IRQ_PSC4_3 (35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IRQ_MAC_MACE_DMA IRQ_PSC4_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* OSS Level 4 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IRQ_MAC_SCC (33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Level 5 (PSC, AV Macs only) interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IRQ_PSC5_0 (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IRQ_PSC5_1 (41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IRQ_PSC5_2 (42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IRQ_PSC5_3 (43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Level 6 (PSC, AV Macs only) interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IRQ_PSC6_0 (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IRQ_PSC6_1 (49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IRQ_PSC6_2 (50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IRQ_PSC6_3 (51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Nubus interrupts (cascaded to VIA2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IRQ_NUBUS_9 (56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IRQ_NUBUS_A (57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IRQ_NUBUS_B (58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IRQ_NUBUS_C (59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IRQ_NUBUS_D (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IRQ_NUBUS_E (61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IRQ_NUBUS_F (62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Baboon interrupts (cascaded to nubus slot $C) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IRQ_BABOON_0 (64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IRQ_BABOON_1 (65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IRQ_BABOON_2 (66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IRQ_BABOON_3 (67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SLOT2IRQ(x) (x + 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IRQ2SLOT(x) (x - 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #endif /* asm/macints.h */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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