^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * m54xxsim.h -- ColdFire 547x/548x System Integration Unit support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef m54xxsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define m54xxsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CPU_NAME "COLDFIRE(m54xx)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CPU_INSTR_PER_JIFFY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MCF_BUSCLK (MCF_CLK / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MACHINE MACH_M54XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define FPUTYPE FPU_COLDFIRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IOMEMBASE MCF_MBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IOMEMSIZE 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/m54xxacr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MCFINT_VECBASE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Interrupt Controller Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCFINTC_IRLR 0x18 /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCFINTC_IACKL 0x19 /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCFINTC_ICR0 0x40 /* Base ICR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * UART module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Define system peripheral IRQ usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MCF_IRQ_I2C0 (MCFINT_VECBASE + 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MCF_IRQ_UART0 (MCFINT_VECBASE + 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MCF_IRQ_UART1 (MCFINT_VECBASE + 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Slice Timer support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Generic GPIO support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MCFGPIO_PODR (MCF_MBAR + 0xA00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MCFGPIO_PDDR (MCF_MBAR + 0xA10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MCFGPIO_PPDR (MCF_MBAR + 0xA20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MCFGPIO_SETR (MCF_MBAR + 0xA20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MCFGPIO_CLRR (MCF_MBAR + 0xA30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MCFGPIO_PIN_MAX 136 /* 128 gpio + 8 eport */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MCFGPIO_IRQ_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * EDGE Port support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Pin Assignment register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MCF_PAR_SDA (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MCF_PAR_SCL (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MCF_PAR_PSC_TXD (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MCF_PAR_PSC_RXD (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MCF_PAR_PSC_CTS_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MCF_PAR_PSC_CTS_BCLK (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MCF_PAR_PSC_CTS_CTS (0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCF_PAR_PSC_RTS_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MCF_PAR_PSC_RTS_FSYNC (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MCF_PAR_PSC_RTS_RTS (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MCF_PAR_PSC_CANRX (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MCF_PAR_FECI2CIRQ (MCF_MBAR + 0x00000a44) /* FEC/I2C/IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MCF_PAR_FECI2CIRQ_SDA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCF_PAR_FECI2CIRQ_SCL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * I2C module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MCFI2C_BASE0 (MCF_MBAR + 0x8f00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MCFI2C_SIZE0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif /* m54xxsim_h */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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