^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * m54xxpci.h -- ColdFire 547x and 548x PCI bus support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef M54XXPCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define M54XXPCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * The core set of PCI support registers are mapped into the MBAR region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCICR2 (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCIGSCR (CONFIG_MBAR + 0xb60) /* Global status/control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCITBATR0 (CONFIG_MBAR + 0xb64) /* Target base translation 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCITBATR1 (CONFIG_MBAR + 0xb68) /* Target base translation 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCITCR (CONFIG_MBAR + 0xb6c) /* Target control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCIIW0BTAR (CONFIG_MBAR + 0xb70) /* Initiator window 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCIIW1BTAR (CONFIG_MBAR + 0xb74) /* Initiator window 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCIIW2BTAR (CONFIG_MBAR + 0xb78) /* Initiator window 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCIIWCR (CONFIG_MBAR + 0xb80) /* Initiator window config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCIICR (CONFIG_MBAR + 0xb84) /* Initiator control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCIISR (CONFIG_MBAR + 0xb88) /* Initiator status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCICAR (CONFIG_MBAR + 0xbf8) /* Configuration address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCIRPSR (CONFIG_MBAR + 0x8480) /* RX packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCIRSAR (CONFIG_MBAR + 0x8484) /* RX start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCIRTCR (CONFIG_MBAR + 0x8488) /* RX transaction control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCIRER (CONFIG_MBAR + 0x848c) /* RX enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCIRNAR (CONFIG_MBAR + 0x8490) /* RX next address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCIRDCR (CONFIG_MBAR + 0x8498) /* RX done counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCIRSR (CONFIG_MBAR + 0x849c) /* RX status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCIRFDR (CONFIG_MBAR + 0x84c0) /* RX FIFO data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCIRFSR (CONFIG_MBAR + 0x84c4) /* RX FIFO status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCIRFCR (CONFIG_MBAR + 0x84c8) /* RX FIFO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCIRFAR (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCIRFRPR (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PASR (CONFIG_MBAR + 0xc04) /* PCI arbiter status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Definitions for the Global status and control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PCIGSCR_PE 0x20000000 /* Parity error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCIGSCR_SE 0x10000000 /* System error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PCIGSCR_XCLKBIN 0x07000000 /* XLB2CLKIN mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCIGSCR_PEE 0x00002000 /* Parity error intr enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCIGSCR_SEE 0x00001000 /* System error intr enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCIGSCR_RESET 0x00000001 /* Reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Bit definitions for the PCICAR configuration address register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PCICAR_E 0x80000000 /* Enable config space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PCICAR_BUSN 16 /* Move bus bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PCICAR_DEVFNN 8 /* Move devfn bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PCICAR_DWORDN 0 /* Move dword bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * The initiator windows hold the memory and IO mapping information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * This macro creates the register values from the desired addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define WXBTAR(hostaddr, pciaddr, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) (((hostaddr) & 0xff000000) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ((((size) - 1) & 0xff000000) >> 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (((pciaddr) & 0xff000000) >> 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCIIWCR_W0_MEM 0x00000000 /* Window 0 is memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCIIWCR_W0_IO 0x08000000 /* Window 0 is IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PCIIWCR_W0_MRD 0x00000000 /* Window 0 memory read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCIIWCR_W0_MRDL 0x02000000 /* Window 0 memory read line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCIIWCR_W0_MRDM 0x04000000 /* Window 0 memory read mult */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PCIIWCR_W0_E 0x01000000 /* Window 0 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PCIIWCR_W1_MEM 0x00000000 /* Window 0 is memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCIIWCR_W1_IO 0x00080000 /* Window 0 is IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCIIWCR_W1_MRD 0x00000000 /* Window 0 memory read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCIIWCR_W1_MRDL 0x00020000 /* Window 0 memory read line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCIIWCR_W1_MRDM 0x00040000 /* Window 0 memory read mult */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCIIWCR_W1_E 0x00010000 /* Window 0 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Bit definitions for the PCIBATR registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCITBATR0_E 0x00000001 /* Enable window 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PCITBATR1_E 0x00000001 /* Enable window 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * PCI arbiter support definitions and macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PACR_INTMPRI 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PACR_EXTMPRI(x) (((x) & 0x1f) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PACR_INTMINTE 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PACR_EXTMINTE(x) (((x) & 0x1f) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PACR_PKMD 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PACR_DS 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PCICR1_CL(x) ((x) & 0xf) /* Cacheline size field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PCICR1_LT(x) (((x) & 0xff) << 8) /* Latency timer field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif /* M54XXPCI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags