Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *	m5441xsim.h -- Coldfire 5441x register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	(C) Copyright 2012, Steven King <sfking@fdwdc.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef m5441xsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define m5441xsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define CPU_NAME		"COLDFIRE(m5441x)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define CPU_INSTR_PER_JIFFY	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define MCF_BUSCLK		(MCF_CLK / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define MACHINE			MACH_M5441X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define FPUTYPE			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define IOMEMBASE		0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IOMEMSIZE		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/m54xxacr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *  Reset Controller Module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define	MCF_RCR			0xec090000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define	MCF_RSR			0xec090001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *  Interrupt Controller Modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* the 5441x have 3 interrupt controllers, each control 64 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MCFINT_VECBASE		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MCFINT0_VECBASE		MCFINT_VECBASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MCFINT1_VECBASE		(MCFINT0_VECBASE + 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MCFINT2_VECBASE		(MCFINT1_VECBASE + 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* interrupt controller 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MCFINTC0_SIMR		0xfc04801c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MCFINTC0_CIMR		0xfc04801d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define	MCFINTC0_ICR0		0xfc048040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* interrupt controller 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MCFINTC1_SIMR		0xfc04c01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MCFINTC1_CIMR		0xfc04c01d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define	MCFINTC1_ICR0		0xfc04c040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* interrupt controller 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MCFINTC2_SIMR		0xfc05001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MCFINTC2_CIMR		0xfc05001d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define	MCFINTC2_ICR0		0xfc050040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* on interrupt controller 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MCFINT0_EPORT0		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MCFINT0_UART0		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MCFINT0_UART1		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MCFINT0_UART2		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MCFINT0_UART3		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MCFINT0_I2C0		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MCFINT0_DSPI0		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MCFINT0_TIMER0		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MCFINT0_TIMER1		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MCFINT0_TIMER2		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MCFINT0_TIMER3		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MCFINT0_FECRX0		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MCFINT0_FECTX0		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MCFINT0_FECENTC0	42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MCFINT0_FECRX1		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MCFINT0_FECTX1		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MCFINT0_FECENTC1	55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* on interrupt controller 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define MCFINT1_UART4		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MCFINT1_UART5		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MCFINT1_UART6		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MCFINT1_UART7		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MCFINT1_UART8		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MCFINT1_UART9		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MCFINT1_DSPI1		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MCFINT1_DSPI2		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define MCFINT1_DSPI3		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define MCFINT1_I2C1		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MCFINT1_I2C2		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MCFINT1_I2C3		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MCFINT1_I2C4		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define MCFINT1_I2C5		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* on interrupt controller 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define MCFINT2_PIT0		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define MCFINT2_PIT1		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MCFINT2_PIT2		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MCFINT2_PIT3		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define MCFINT2_RTC		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  *  PIT timer module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define	MCFPIT_BASE0		0xFC080000	/* Base address of TIMER0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define	MCFPIT_BASE1		0xFC084000	/* Base address of TIMER1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define	MCFPIT_BASE2		0xFC088000	/* Base address of TIMER2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define	MCFPIT_BASE3		0xFC08C000	/* Base address of TIMER3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCF_IRQ_PIT1		(MCFINT2_VECBASE + MCFINT2_PIT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * Power Management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MCFPM_WCR		0xfc040013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MCFPM_PPMSR0		0xfc04002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCFPM_PPMCR0		0xfc04002d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MCFPM_PPMSR1		0xfc04002e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MCFPM_PPMCR1		0xfc04002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MCFPM_PPMHR0		0xfc040030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MCFPM_PPMLR0		0xfc040034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MCFPM_PPMHR1		0xfc040038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MCFPM_PPMLR1		0xfc04003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MCFPM_LPCR		0xec090007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  *  UART module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MCFUART_BASE0		0xfc060000	/* Base address of UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MCFUART_BASE1		0xfc064000	/* Base address of UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MCFUART_BASE2		0xfc068000	/* Base address of UART2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MCFUART_BASE3		0xfc06c000	/* Base address of UART3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MCFUART_BASE4		0xec060000	/* Base address of UART4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MCFUART_BASE5		0xec064000	/* Base address of UART5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MCFUART_BASE6		0xec068000	/* Base address of UART6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MCFUART_BASE7		0xec06c000	/* Base address of UART7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MCFUART_BASE8		0xec070000	/* Base address of UART8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCFUART_BASE9		0xec074000	/* Base address of UART9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MCF_IRQ_UART0		(MCFINT0_VECBASE + MCFINT0_UART0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MCF_IRQ_UART1		(MCFINT0_VECBASE + MCFINT0_UART1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MCF_IRQ_UART2		(MCFINT0_VECBASE + MCFINT0_UART2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MCF_IRQ_UART3		(MCFINT0_VECBASE + MCFINT0_UART3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MCF_IRQ_UART4		(MCFINT1_VECBASE + MCFINT1_UART4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MCF_IRQ_UART5		(MCFINT1_VECBASE + MCFINT1_UART5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MCF_IRQ_UART6		(MCFINT1_VECBASE + MCFINT1_UART6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MCF_IRQ_UART7		(MCFINT1_VECBASE + MCFINT1_UART7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MCF_IRQ_UART8		(MCFINT1_VECBASE + MCFINT1_UART8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MCF_IRQ_UART9		(MCFINT1_VECBASE + MCFINT1_UART9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  *  FEC modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MCFFEC_BASE0		0xfc0d4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MCFFEC_SIZE0		0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MCF_IRQ_FECRX0		(MCFINT0_VECBASE + MCFINT0_FECRX0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MCF_IRQ_FECTX0		(MCFINT0_VECBASE + MCFINT0_FECTX0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MCF_IRQ_FECENTC0	(MCFINT0_VECBASE + MCFINT0_FECENTC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MCFFEC_BASE1		0xfc0d8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MCFFEC_SIZE1		0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MCF_IRQ_FECRX1		(MCFINT0_VECBASE + MCFINT0_FECRX1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MCF_IRQ_FECTX1		(MCFINT0_VECBASE + MCFINT0_FECTX1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MCF_IRQ_FECENTC1	(MCFINT0_VECBASE + MCFINT0_FECENTC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  *  I2C modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MCFI2C_BASE0		0xfc058000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MCFI2C_SIZE0		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MCFI2C_BASE1		0xfc038000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MCFI2C_SIZE1		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MCFI2C_BASE2		0xec010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MCFI2C_SIZE2		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MCFI2C_BASE3		0xec014000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MCFI2C_SIZE3		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MCFI2C_BASE4		0xec018000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MCFI2C_SIZE4		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MCFI2C_BASE5		0xec01c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MCFI2C_SIZE5		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MCF_IRQ_I2C0		(MCFINT0_VECBASE + MCFINT0_I2C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MCF_IRQ_I2C1		(MCFINT1_VECBASE + MCFINT1_I2C1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MCF_IRQ_I2C2		(MCFINT1_VECBASE + MCFINT1_I2C2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MCF_IRQ_I2C3		(MCFINT1_VECBASE + MCFINT1_I2C3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MCF_IRQ_I2C4		(MCFINT1_VECBASE + MCFINT1_I2C4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MCF_IRQ_I2C5		(MCFINT1_VECBASE + MCFINT1_I2C5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  *  EPORT Module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MCFEPORT_EPPAR		0xfc090000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MCFEPORT_EPIER		0xfc090003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MCFEPORT_EPFR		0xfc090006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  *  RTC Module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MCFRTC_BASE		0xfc0a8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MCFRTC_SIZE		(0xfc0a8840 - 0xfc0a8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MCF_IRQ_RTC		(MCFINT2_VECBASE + MCFINT2_RTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  *  GPIO Module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MCFGPIO_PODR_A		0xec094000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MCFGPIO_PODR_B		0xec094001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MCFGPIO_PODR_C		0xec094002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MCFGPIO_PODR_D		0xec094003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MCFGPIO_PODR_E		0xec094004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MCFGPIO_PODR_F		0xec094005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MCFGPIO_PODR_G		0xec094006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MCFGPIO_PODR_H		0xec094007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MCFGPIO_PODR_I		0xec094008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MCFGPIO_PODR_J		0xec094009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MCFGPIO_PODR_K		0xec09400a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MCFGPIO_PDDR_A		0xec09400c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MCFGPIO_PDDR_B		0xec09400d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MCFGPIO_PDDR_C		0xec09400e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MCFGPIO_PDDR_D		0xec09400f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MCFGPIO_PDDR_E		0xec094010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MCFGPIO_PDDR_F		0xec094011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MCFGPIO_PDDR_G		0xec094012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MCFGPIO_PDDR_H		0xec094013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MCFGPIO_PDDR_I		0xec094014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MCFGPIO_PDDR_J		0xec094015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MCFGPIO_PDDR_K		0xec094016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MCFGPIO_PPDSDR_A	0xec094018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MCFGPIO_PPDSDR_B	0xec094019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MCFGPIO_PPDSDR_C	0xec09401a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MCFGPIO_PPDSDR_D	0xec09401b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MCFGPIO_PPDSDR_E	0xec09401c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MCFGPIO_PPDSDR_F	0xec09401d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MCFGPIO_PPDSDR_G	0xec09401e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MCFGPIO_PPDSDR_H	0xec09401f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MCFGPIO_PPDSDR_I	0xec094020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MCFGPIO_PPDSDR_J	0xec094021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MCFGPIO_PPDSDR_K	0xec094022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MCFGPIO_PCLRR_A		0xec094024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MCFGPIO_PCLRR_B		0xec094025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MCFGPIO_PCLRR_C		0xec094026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MCFGPIO_PCLRR_D		0xec094027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MCFGPIO_PCLRR_E		0xec094028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MCFGPIO_PCLRR_F		0xec094029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MCFGPIO_PCLRR_G		0xec09402a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MCFGPIO_PCLRR_H		0xec09402b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MCFGPIO_PCLRR_I		0xec09402c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MCFGPIO_PCLRR_J		0xec09402d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MCFGPIO_PCLRR_K		0xec09402e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MCFGPIO_PAR_FBCTL	0xec094048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MCFGPIO_PAR_BE		0xec094049
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MCFGPIO_PAR_CS		0xec09404a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MCFGPIO_PAR_CANI2C	0xec09404b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MCFGPIO_PAR_IRQ0H	0xec09404c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MCFGPIO_PAR_IRQ0L	0xec09404d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MCFGPIO_PAR_DSPIOWH	0xec09404e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MCFGPIO_PAR_DSPIOWL	0xec09404f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MCFGPIO_PAR_TIMER	0xec094050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MCFGPIO_PAR_UART2	0xec094051
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MCFGPIO_PAR_UART1	0xec094052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MCFGPIO_PAR_UART0	0xec094053
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MCFGPIO_PAR_SDHCH	0xec094054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MCFGPIO_PAR_SDHCL	0xec094055
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MCFGPIO_PAR_SIMP0H	0xec094056
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MCFGPIO_PAR_SIMP0L	0xec094057
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MCFGPIO_PAR_SSI0H	0xec094058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MCFGPIO_PAR_SSI0L	0xec094059
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MCFGPIO_PAR_DEBUGH1	0xec09405a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MCFGPIO_PAR_DEBUGH0	0xec09405b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MCFGPIO_PAR_DEBUGl	0xec09405c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MCFGPIO_PAR_FEC		0xec09405e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* generalization for generic gpio support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MCFGPIO_PODR		MCFGPIO_PODR_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MCFGPIO_PDDR		MCFGPIO_PDDR_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MCFGPIO_PPDR		MCFGPIO_PPDSDR_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define MCFGPIO_SETR		MCFGPIO_PPDSDR_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MCFGPIO_CLRR		MCFGPIO_PCLRR_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MCFGPIO_IRQ_MIN		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MCFGPIO_IRQ_MAX		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MCFGPIO_IRQ_VECBASE	(MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define MCFGPIO_PIN_MAX		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  * Phase Locked Loop (PLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define MCF_PLL_CR		0xFC0C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MCF_PLL_DR		0xFC0C0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MCF_PLL_SR		0xFC0C0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  *  DSPI module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MCFDSPI_BASE0		0xfc05c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MCFDSPI_BASE1		0xfC03c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MCF_IRQ_DSPI0		(MCFINT0_VECBASE + MCFINT0_DSPI0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MCF_IRQ_DSPI1		(MCFINT1_VECBASE + MCFINT1_DSPI1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)  *  eDMA module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define MCFEDMA_BASE		0xfc044000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define MCFEDMA_SIZE		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define MCFINT0_EDMA_INTR0	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define MCFINT0_EDMA_ERR	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define MCFEDMA_EDMA_INTR16	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define MCFEDMA_EDMA_INTR56	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MCFEDMA_IRQ_INTR0	(MCFINT0_VECBASE + MCFINT0_EDMA_INTR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MCFEDMA_IRQ_INTR16	(MCFINT1_VECBASE + MCFEDMA_EDMA_INTR16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define MCFEDMA_IRQ_INTR56	(MCFINT2_VECBASE + MCFEDMA_EDMA_INTR56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define MCFEDMA_IRQ_ERR	(MCFINT0_VECBASE + MCFINT0_EDMA_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  *  esdhc module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MCFSDHC_BASE		0xfc0cc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MCFSDHC_SIZE		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MCFINT2_SDHC		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define MCF_IRQ_SDHC		(MCFINT2_VECBASE + MCFINT2_SDHC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define MCFSDHC_CLK		(MCFSDHC_BASE + 0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #endif /* m5441xsim_h */