Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	m5407sim.h -- ColdFire 5407 System Integration Module support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	(C) Copyright 2000,  Lineo (www.lineo.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	(C) Copyright 1999,  Moreton Bay Ventures Pty Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *      Modified by David W. Miller for the MCF5307 Eval Board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #ifndef	m5407sim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define	m5407sim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define	CPU_NAME		"COLDFIRE(m5407)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define	CPU_INSTR_PER_JIFFY	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define	MCF_BUSCLK		(MCF_CLK / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/m54xxacr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *	Define the 5407 SIM register set addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define	MCFSIM_RSR		(MCF_MBAR + 0x00)	/* Reset Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define	MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define	MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog service*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define	MCFSIM_PAR		(MCF_MBAR + 0x04)	/* Pin Assignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define	MCFSIM_IRQPAR		(MCF_MBAR + 0x06)	/* Intr Assignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define	MCFSIM_PLLCR		(MCF_MBAR + 0x08)	/* PLL Ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define	MCFSIM_MPARK		(MCF_MBAR + 0x0C)	/* BUS Master Ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define	MCFSIM_IPR		(MCF_MBAR + 0x40)	/* Interrupt Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define	MCFSIM_IMR		(MCF_MBAR + 0x44)	/* Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define	MCFSIM_AVR		(MCF_MBAR + 0x4b)	/* Autovector Ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define	MCFSIM_ICR0		(MCF_MBAR + 0x4c)	/* Intr Ctrl reg 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	MCFSIM_ICR1		(MCF_MBAR + 0x4d)	/* Intr Ctrl reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define	MCFSIM_ICR2		(MCF_MBAR + 0x4e)	/* Intr Ctrl reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define	MCFSIM_ICR3		(MCF_MBAR + 0x4f)	/* Intr Ctrl reg 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define	MCFSIM_ICR4		(MCF_MBAR + 0x50)	/* Intr Ctrl reg 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define	MCFSIM_ICR5		(MCF_MBAR + 0x51)	/* Intr Ctrl reg 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define	MCFSIM_ICR6		(MCF_MBAR + 0x52)	/* Intr Ctrl reg 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define	MCFSIM_ICR7		(MCF_MBAR + 0x53)	/* Intr Ctrl reg 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define	MCFSIM_ICR8		(MCF_MBAR + 0x54)	/* Intr Ctrl reg 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define	MCFSIM_ICR9		(MCF_MBAR + 0x55)	/* Intr Ctrl reg 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define	MCFSIM_ICR10		(MCF_MBAR + 0x56)	/* Intr Ctrl reg 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define	MCFSIM_ICR11		(MCF_MBAR + 0x57)	/* Intr Ctrl reg 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MCFSIM_CSAR0		(MCF_MBAR + 0x80)	/* CS 0 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MCFSIM_CSMR0		(MCF_MBAR + 0x84)	/* CS 0 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MCFSIM_CSCR0		(MCF_MBAR + 0x8a)	/* CS 0 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MCFSIM_CSAR1		(MCF_MBAR + 0x8c)	/* CS 1 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MCFSIM_CSMR1		(MCF_MBAR + 0x90)	/* CS 1 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MCFSIM_CSCR1		(MCF_MBAR + 0x96)	/* CS 1 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MCFSIM_CSAR2		(MCF_MBAR + 0x98)	/* CS 2 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MCFSIM_CSMR2		(MCF_MBAR + 0x9c)	/* CS 2 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MCFSIM_CSCR2		(MCF_MBAR + 0xa2)	/* CS 2 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MCFSIM_CSAR3		(MCF_MBAR + 0xa4)	/* CS 3 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MCFSIM_CSMR3		(MCF_MBAR + 0xa8)	/* CS 3 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MCFSIM_CSCR3		(MCF_MBAR + 0xae)	/* CS 3 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MCFSIM_CSAR4		(MCF_MBAR + 0xb0)	/* CS 4 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MCFSIM_CSMR4		(MCF_MBAR + 0xb4)	/* CS 4 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MCFSIM_CSCR4		(MCF_MBAR + 0xba)	/* CS 4 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MCFSIM_CSAR5		(MCF_MBAR + 0xbc)	/* CS 5 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MCFSIM_CSMR5		(MCF_MBAR + 0xc0)	/* CS 5 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MCFSIM_CSCR5		(MCF_MBAR + 0xc6)	/* CS 5 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MCFSIM_CSAR6		(MCF_MBAR + 0xc8)	/* CS 6 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MCFSIM_CSMR6		(MCF_MBAR + 0xcc)	/* CS 6 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MCFSIM_CSCR6		(MCF_MBAR + 0xd2)	/* CS 6 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MCFSIM_CSAR7		(MCF_MBAR + 0xd4)	/* CS 7 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MCFSIM_CSMR7		(MCF_MBAR + 0xd8)	/* CS 7 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MCFSIM_CSCR7		(MCF_MBAR + 0xde)	/* CS 7 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MCFSIM_DACR0		(MCF_MBAR + 0x108)	/* DRAM 0 Addr/Ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MCFSIM_DMR0		(MCF_MBAR + 0x10c)	/* DRAM 0 Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MCFSIM_DACR1		(MCF_MBAR + 0x110)	/* DRAM 1 Addr/Ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MCFSIM_DMR1		(MCF_MBAR + 0x114)	/* DRAM 1 Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  *	Timer module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MCFTIMER_BASE1		(MCF_MBAR + 0x140)	/* Base of TIMER1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MCFTIMER_BASE2		(MCF_MBAR + 0x180)	/* Base of TIMER2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define MCFUART_BASE0		(MCF_MBAR + 0x1c0)	/* Base address UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MCFUART_BASE1		(MCF_MBAR + 0x200)	/* Base address UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define	MCFSIM_PADDR		(MCF_MBAR + 0x244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define	MCFSIM_PADAT		(MCF_MBAR + 0x248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  *	DMA unit base addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MCFDMA_BASE0		(MCF_MBAR + 0x300)	/* Base address DMA 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define MCFDMA_BASE1		(MCF_MBAR + 0x340)	/* Base address DMA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MCFDMA_BASE2		(MCF_MBAR + 0x380)	/* Base address DMA 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * Generic GPIO support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MCFGPIO_PIN_MAX		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCFGPIO_IRQ_MAX		-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MCFGPIO_IRQ_VECBASE	-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  *	Some symbol defines for the above...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define	MCFSIM_SWDICR		MCFSIM_ICR0	/* Watchdog timer ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define	MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define	MCFSIM_TIMER2ICR	MCFSIM_ICR2	/* Timer 2 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define	MCFSIM_I2CICR		MCFSIM_ICR3	/* I2C ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define	MCFSIM_UART1ICR		MCFSIM_ICR4	/* UART 1 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define	MCFSIM_UART2ICR		MCFSIM_ICR5	/* UART 2 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define	MCFSIM_DMA0ICR		MCFSIM_ICR6	/* DMA 0 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define	MCFSIM_DMA1ICR		MCFSIM_ICR7	/* DMA 1 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define	MCFSIM_DMA2ICR		MCFSIM_ICR8	/* DMA 2 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define	MCFSIM_DMA3ICR		MCFSIM_ICR9	/* DMA 3 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  *	Some symbol defines for the Parallel Port Pin Assignment Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MCFSIM_PAR_DREQ0        0x40            /* Set to select DREQ0 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)                                                 /* Clear to select par I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MCFSIM_PAR_DREQ1        0x20            /* Select DREQ1 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)                                                 /* Clear to select par I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  *       Defines for the IRQPAR Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IRQ5_LEVEL4		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IRQ3_LEVEL6		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IRQ1_LEVEL2		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  *	Define system peripheral IRQ usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define	MCF_IRQ_I2C0		29		/* I2C, Level 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define	MCF_IRQ_TIMER		30		/* Timer0, Level 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define	MCF_IRQ_PROFILER	31		/* Timer1, Level 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define	MCF_IRQ_UART0		73		/* UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define	MCF_IRQ_UART1		74		/* UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * I2C module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define	MCFI2C_BASE0		(MCF_MBAR + 0x280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define	MCFI2C_SIZE0		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif	/* m5407sim_h */