^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * m53xxsim.h -- ColdFire 5329 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef m53xxsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define m53xxsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CPU_NAME "COLDFIRE(m53xx)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CPU_INSTR_PER_JIFFY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MCF_BUSCLK (MCF_CLK / 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/m53xxacr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MCFINT_VECBASE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MCFINT_UART0 26 /* Interrupt number for UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MCFINT_UART1 27 /* Interrupt number for UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MCFINT_UART2 28 /* Interrupt number for UART2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MCFINT_I2C0 30 /* Interrupt number for I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MCFINT_QSPI 31 /* Interrupt number for QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MCFINT_FECRX0 36 /* Interrupt number for FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MCFINT_FECTX0 40 /* Interrupt number for FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MCFINT_FECENTC0 42 /* Interrupt number for FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MCF_WTM_WCR 0xFC098000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Define the 532x SIM register set addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MCFSIM_IPRL 0xFC048004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MCFSIM_IPRH 0xFC048000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCFSIM_IPR MCFSIM_IPRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MCFSIM_IMRL 0xFC04800C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MCFSIM_IMRH 0xFC048008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MCFSIM_IMR MCFSIM_IMRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MCFSIM_ICR0 0xFC048040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MCFSIM_ICR1 0xFC048041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MCFSIM_ICR2 0xFC048042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MCFSIM_ICR3 0xFC048043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MCFSIM_ICR4 0xFC048044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MCFSIM_ICR5 0xFC048045
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MCFSIM_ICR6 0xFC048046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MCFSIM_ICR7 0xFC048047
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MCFSIM_ICR8 0xFC048048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MCFSIM_ICR9 0xFC048049
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MCFSIM_ICR10 0xFC04804A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MCFSIM_ICR11 0xFC04804B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Some symbol defines for the above...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MCFINTC0_SIMR 0xFC04801C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MCFINTC0_CIMR 0xFC04801D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MCFINTC0_ICR0 0xFC048040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MCFINTC1_SIMR 0xFC04C01C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MCFINTC1_CIMR 0xFC04C01D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MCFINTC1_ICR0 0xFC04C040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MCFINTC2_SIMR (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MCFINTC2_CIMR (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MCFINTC2_ICR0 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MCFSIM_ICR_TIMER1 (0xFC048040+32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MCFSIM_ICR_TIMER2 (0xFC048040+33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Define system peripheral IRQ usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MCF_IRQ_TIMER (64 + 32) /* Timer0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * UART module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * FEC module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * QSPI module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MCFQSPI_BASE 0xFC05C000 /* Base address of QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCFQSPI_SIZE 0x40 /* Size of QSPI region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MCFQSPI_CS0 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MCFQSPI_CS1 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MCFQSPI_CS2 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Timer module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Reset Controller Module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCF_RCR 0xFC0A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MCF_RSR 0xFC0A0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MCF_RCR_SWRESET 0x80 /* Software reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Power Management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MCFPM_WCR 0xfc040013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MCFPM_PPMSR0 0xfc04002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MCFPM_PPMCR0 0xfc04002d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MCFPM_PPMSR1 0xfc04002e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MCFPM_PPMCR1 0xfc04002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MCFPM_PPMHR0 0xfc040030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MCFPM_PPMLR0 0xfc040034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MCFPM_PPMHR1 0xfc040038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MCFPM_LPCR 0xec090007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * The M5329EVB board needs a help getting its devices initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * at kernel start time if dBUG doesn't set it up (for example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * it is not used), so we need to do it manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #ifdef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .macro m5329EVB_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) movel #0xFC098000, %a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) movel #0x0, (%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CORE_SRAM 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CORE_SRAM_SIZE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) movel #CORE_SRAM, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) addl #0x221, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) movec %d0,%RAMBAR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) movel #CORE_SRAM, %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) addl #CORE_SRAM_SIZE, %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) jsr sysinit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PLATFORM_SETUP m5329EVB_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif /* __ASSEMBLER__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Chip Configuration Module (CCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Register read/write macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MCF_CCM_CCR 0xFC0A0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MCF_CCM_RCON 0xFC0A0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MCF_CCM_CIR 0xFC0A000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MCF_CCM_MISCCR 0xFC0A0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MCF_CCM_CDR 0xFC0A0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MCF_CCM_UHCSR 0xFC0A0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MCF_CCM_UOCSR 0xFC0A0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Bit definitions and macros for MCF_CCM_CCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MCF_CCM_CCR_RESERVED (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MCF_CCM_CCR_PLL_MODE (0x0003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MCF_CCM_CCR_OSC_MODE (0x0005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MCF_CCM_CCR_LOAD (0x0021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MCF_CCM_CCR_LIMP (0x0041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Bit definitions and macros for MCF_CCM_RCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MCF_CCM_RCON_RESERVED (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MCF_CCM_RCON_PLL_MODE (0x0003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MCF_CCM_RCON_OSC_MODE (0x0005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MCF_CCM_RCON_LOAD (0x0021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MCF_CCM_RCON_LIMP (0x0041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Bit definitions and macros for MCF_CCM_CIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Bit definitions and macros for MCF_CCM_MISCCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MCF_CCM_MISCCR_USBSRC (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MCF_CCM_MISCCR_USBDIV (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MCF_CCM_MISCCR_SSI_SRC (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MCF_CCM_MISCCR_TIM_DMA (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MCF_CCM_MISCCR_SSI_PUS (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MCF_CCM_MISCCR_SSI_PUE (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MCF_CCM_MISCCR_LCD_CHEN (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MCF_CCM_MISCCR_LIMP (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MCF_CCM_MISCCR_PLL_LOCK (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Bit definitions and macros for MCF_CCM_CDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Bit definitions and macros for MCF_CCM_UHCSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MCF_CCM_UHCSR_XPDE (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MCF_CCM_UHCSR_UHMIE (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MCF_CCM_UHCSR_WKUP (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Bit definitions and macros for MCF_CCM_UOCSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MCF_CCM_UOCSR_XPDE (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MCF_CCM_UOCSR_UOMIE (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MCF_CCM_UOCSR_WKUP (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MCF_CCM_UOCSR_PWRFLT (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MCF_CCM_UOCSR_SEND (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MCF_CCM_UOCSR_VVLD (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MCF_CCM_UOCSR_BVLD (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MCF_CCM_UOCSR_AVLD (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MCF_CCM_UOCSR_DPPU (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MCF_CCM_UOCSR_DCR_VBUS (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MCF_CCM_UOCSR_CRG_VBUS (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MCF_CCM_UOCSR_DRV_VBUS (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MCF_CCM_UOCSR_DMPD (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MCF_CCM_UOCSR_DPPD (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * FlexBus Chip Selects (FBCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Register read/write macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MCF_FBCS0_CSAR 0xFC008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MCF_FBCS0_CSMR 0xFC008004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MCF_FBCS0_CSCR 0xFC008008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MCF_FBCS1_CSAR 0xFC00800C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MCF_FBCS1_CSMR 0xFC008010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MCF_FBCS1_CSCR 0xFC008014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MCF_FBCS2_CSAR 0xFC008018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MCF_FBCS2_CSMR 0xFC00801C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MCF_FBCS2_CSCR 0xFC008020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MCF_FBCS3_CSAR 0xFC008024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define MCF_FBCS3_CSMR 0xFC008028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MCF_FBCS3_CSCR 0xFC00802C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MCF_FBCS4_CSAR 0xFC008030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MCF_FBCS4_CSMR 0xFC008034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MCF_FBCS4_CSCR 0xFC008038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define MCF_FBCS5_CSAR 0xFC00803C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MCF_FBCS5_CSMR 0xFC008040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MCF_FBCS5_CSCR 0xFC008044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Bit definitions and macros for MCF_FBCS_CSAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Bit definitions and macros for MCF_FBCS_CSMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MCF_FBCS_CSMR_V (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define MCF_FBCS_CSMR_WP (0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define MCF_FBCS_CSMR_BAM_512K (0x00070000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define MCF_FBCS_CSMR_BAM_256K (0x00030000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define MCF_FBCS_CSMR_BAM_128K (0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define MCF_FBCS_CSMR_BAM_64K (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Bit definitions and macros for MCF_FBCS_CSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MCF_FBCS_CSCR_BSTW (0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define MCF_FBCS_CSCR_BSTR (0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define MCF_FBCS_CSCR_BEM (0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define MCF_FBCS_CSCR_AA (0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define MCF_FBCS_CSCR_SBM (0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define MCF_FBCS_CSCR_SWSEN (0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define MCF_FBCS_CSCR_PS_8 (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define MCF_FBCS_CSCR_PS_16 (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define MCF_FBCS_CSCR_PS_32 (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * General Purpose I/O (GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Register read/write macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define MCFGPIO_PODR_FECH (0xFC0A4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define MCFGPIO_PODR_FECL (0xFC0A4001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MCFGPIO_PODR_SSI (0xFC0A4002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MCFGPIO_PODR_BUSCTL (0xFC0A4003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define MCFGPIO_PODR_BE (0xFC0A4004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MCFGPIO_PODR_CS (0xFC0A4005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define MCFGPIO_PODR_PWM (0xFC0A4006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define MCFGPIO_PODR_FECI2C (0xFC0A4007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MCFGPIO_PODR_UART (0xFC0A4009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define MCFGPIO_PODR_QSPI (0xFC0A400A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define MCFGPIO_PODR_TIMER (0xFC0A400B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define MCFGPIO_PODR_LCDDATAH (0xFC0A400D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define MCFGPIO_PODR_LCDDATAM (0xFC0A400E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define MCFGPIO_PODR_LCDDATAL (0xFC0A400F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define MCFGPIO_PODR_LCDCTLH (0xFC0A4010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define MCFGPIO_PODR_LCDCTLL (0xFC0A4011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define MCFGPIO_PDDR_FECH (0xFC0A4014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define MCFGPIO_PDDR_FECL (0xFC0A4015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define MCFGPIO_PDDR_SSI (0xFC0A4016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define MCFGPIO_PDDR_BUSCTL (0xFC0A4017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define MCFGPIO_PDDR_BE (0xFC0A4018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define MCFGPIO_PDDR_CS (0xFC0A4019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define MCFGPIO_PDDR_PWM (0xFC0A401A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define MCFGPIO_PDDR_FECI2C (0xFC0A401B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define MCFGPIO_PDDR_UART (0xFC0A401C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define MCFGPIO_PDDR_QSPI (0xFC0A401E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define MCFGPIO_PDDR_TIMER (0xFC0A401F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define MCFGPIO_PDDR_LCDDATAH (0xFC0A4021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define MCFGPIO_PDDR_LCDDATAM (0xFC0A4022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define MCFGPIO_PDDR_LCDDATAL (0xFC0A4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MCFGPIO_PDDR_LCDCTLH (0xFC0A4024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define MCFGPIO_PDDR_LCDCTLL (0xFC0A4025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define MCFGPIO_PPDSDR_FECH (0xFC0A4028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define MCFGPIO_PPDSDR_FECL (0xFC0A4029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define MCFGPIO_PPDSDR_SSI (0xFC0A402A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define MCFGPIO_PPDSDR_BUSCTL (0xFC0A402B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define MCFGPIO_PPDSDR_BE (0xFC0A402C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define MCFGPIO_PPDSDR_CS (0xFC0A402D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MCFGPIO_PPDSDR_PWM (0xFC0A402E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define MCFGPIO_PPDSDR_FECI2C (0xFC0A402F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define MCFGPIO_PPDSDR_UART (0xFC0A4031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define MCFGPIO_PPDSDR_QSPI (0xFC0A4032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define MCFGPIO_PPDSDR_TIMER (0xFC0A4033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define MCFGPIO_PPDSDR_LCDDATAH (0xFC0A4035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define MCFGPIO_PPDSDR_LCDDATAM (0xFC0A4036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define MCFGPIO_PPDSDR_LCDDATAL (0xFC0A4037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define MCFGPIO_PPDSDR_LCDCTLH (0xFC0A4038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define MCFGPIO_PPDSDR_LCDCTLL (0xFC0A4039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define MCFGPIO_PCLRR_FECH (0xFC0A403C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define MCFGPIO_PCLRR_FECL (0xFC0A403D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define MCFGPIO_PCLRR_SSI (0xFC0A403E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define MCFGPIO_PCLRR_BUSCTL (0xFC0A403F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define MCFGPIO_PCLRR_BE (0xFC0A4040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define MCFGPIO_PCLRR_CS (0xFC0A4041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define MCFGPIO_PCLRR_PWM (0xFC0A4042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define MCFGPIO_PCLRR_FECI2C (0xFC0A4043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define MCFGPIO_PCLRR_UART (0xFC0A4045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define MCFGPIO_PCLRR_QSPI (0xFC0A4046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define MCFGPIO_PCLRR_TIMER (0xFC0A4047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define MCFGPIO_PCLRR_LCDDATAH (0xFC0A4049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define MCFGPIO_PCLRR_LCDDATAM (0xFC0A404A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define MCFGPIO_PAR_FEC (0xFC0A4050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define MCFGPIO_PAR_PWM (0xFC0A4051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define MCFGPIO_PAR_BUSCTL (0xFC0A4052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define MCFGPIO_PAR_FECI2C (0xFC0A4053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define MCFGPIO_PAR_BE (0xFC0A4054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define MCFGPIO_PAR_CS (0xFC0A4055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define MCFGPIO_PAR_SSI (0xFC0A4056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define MCFGPIO_PAR_UART (0xFC0A4058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define MCFGPIO_PAR_QSPI (0xFC0A405A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define MCFGPIO_PAR_TIMER (0xFC0A405C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define MCFGPIO_PAR_LCDDATA (0xFC0A405D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define MCFGPIO_PAR_LCDCTL (0xFC0A405E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define MCFGPIO_PAR_IRQ (0xFC0A4060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define MCFGPIO_MSCR_FLEXBUS (0xFC0A4064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define MCFGPIO_MSCR_SDRAM (0xFC0A4065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define MCFGPIO_DSCR_I2C (0xFC0A4068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define MCFGPIO_DSCR_PWM (0xFC0A4069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define MCFGPIO_DSCR_FEC (0xFC0A406A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define MCFGPIO_DSCR_UART (0xFC0A406B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define MCFGPIO_DSCR_QSPI (0xFC0A406C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define MCFGPIO_DSCR_TIMER (0xFC0A406D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define MCFGPIO_DSCR_SSI (0xFC0A406E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define MCFGPIO_DSCR_LCD (0xFC0A406F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define MCFGPIO_DSCR_DEBUG (0xFC0A4070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MCFGPIO_DSCR_CLKRST (0xFC0A4071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define MCFGPIO_DSCR_IRQ (0xFC0A4072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Bit definitions and macros for MCF_GPIO_PODR_FECH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Bit definitions and macros for MCF_GPIO_PODR_FECL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Bit definitions and macros for MCF_GPIO_PODR_SSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Bit definitions and macros for MCF_GPIO_PODR_BE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define MCF_GPIO_PODR_BE_PODR_BE0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define MCF_GPIO_PODR_BE_PODR_BE1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define MCF_GPIO_PODR_BE_PODR_BE2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define MCF_GPIO_PODR_BE_PODR_BE3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Bit definitions and macros for MCF_GPIO_PODR_CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define MCF_GPIO_PODR_CS_PODR_CS1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define MCF_GPIO_PODR_CS_PODR_CS2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define MCF_GPIO_PODR_CS_PODR_CS3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define MCF_GPIO_PODR_CS_PODR_CS4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define MCF_GPIO_PODR_CS_PODR_CS5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* Bit definitions and macros for MCF_GPIO_PODR_PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Bit definitions and macros for MCF_GPIO_PODR_UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define MCF_GPIO_PODR_UART_PODR_UART0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define MCF_GPIO_PODR_UART_PODR_UART1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define MCF_GPIO_PODR_UART_PODR_UART2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define MCF_GPIO_PODR_UART_PODR_UART3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define MCF_GPIO_PODR_UART_PODR_UART4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define MCF_GPIO_PODR_UART_PODR_UART5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define MCF_GPIO_PODR_UART_PODR_UART6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define MCF_GPIO_PODR_UART_PODR_UART7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Bit definitions and macros for MCF_GPIO_PDDR_FECH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* Bit definitions and macros for MCF_GPIO_PDDR_FECL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Bit definitions and macros for MCF_GPIO_PDDR_SSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Bit definitions and macros for MCF_GPIO_PDDR_BE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Bit definitions and macros for MCF_GPIO_PDDR_CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Bit definitions and macros for MCF_GPIO_PDDR_PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* Bit definitions and macros for MCF_GPIO_PDDR_UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* Bit definitions and macros for MCF_GPIO_PCLRR_BE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Bit definitions and macros for MCF_GPIO_PCLRR_UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* Bit definitions and macros for MCF_GPIO_PAR_FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* Bit definitions and macros for MCF_GPIO_PAR_PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* Bit definitions and macros for MCF_GPIO_PAR_BE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define MCF_GPIO_PAR_BE_PAR_BE0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define MCF_GPIO_PAR_BE_PAR_BE1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define MCF_GPIO_PAR_BE_PAR_BE2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define MCF_GPIO_PAR_BE_PAR_BE3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Bit definitions and macros for MCF_GPIO_PAR_CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define MCF_GPIO_PAR_CS_PAR_CS1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define MCF_GPIO_PAR_CS_PAR_CS3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define MCF_GPIO_PAR_CS_PAR_CS4 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define MCF_GPIO_PAR_CS_PAR_CS5 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* Bit definitions and macros for MCF_GPIO_PAR_SSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* Bit definitions and macros for MCF_GPIO_PAR_UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* Bit definitions and macros for MCF_GPIO_PAR_IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* Bit definitions and macros for MCF_GPIO_DSCR_I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* Bit definitions and macros for MCF_GPIO_DSCR_PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* Bit definitions and macros for MCF_GPIO_DSCR_FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* Bit definitions and macros for MCF_GPIO_DSCR_UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* Bit definitions and macros for MCF_GPIO_DSCR_SSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* Bit definitions and macros for MCF_GPIO_DSCR_LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * Generic GPIO support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define MCFGPIO_PODR MCFGPIO_PODR_FECH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define MCFGPIO_PDDR MCFGPIO_PDDR_FECH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define MCFGPIO_PPDR MCFGPIO_PPDSDR_FECH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define MCFGPIO_SETR MCFGPIO_PPDSDR_FECH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define MCFGPIO_CLRR MCFGPIO_PCLRR_FECH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define MCFGPIO_PIN_MAX 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define MCFGPIO_IRQ_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * Phase Locked Loop (PLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) *********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* Register read/write macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define MCF_PLL_PODR 0xFC0C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define MCF_PLL_PLLCR 0xFC0C0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define MCF_PLL_PMDR 0xFC0C0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define MCF_PLL_PFDR 0xFC0C000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* Bit definitions and macros for MCF_PLL_PODR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* Bit definitions and macros for MCF_PLL_PLLCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define MCF_PLL_PLLCR_DITHEN (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* Bit definitions and macros for MCF_PLL_PMDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* Bit definitions and macros for MCF_PLL_PFDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * System Control Module Registers (SCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) *********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* Register read/write macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define MCF_SCM_MPR 0xFC000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define MCF_SCM_PACRA 0xFC000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define MCF_SCM_PACRB 0xFC000024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define MCF_SCM_PACRC 0xFC000028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define MCF_SCM_PACRD 0xFC00002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define MCF_SCM_PACRE 0xFC000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define MCF_SCM_PACRF 0xFC000044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define MCF_SCM_BCR 0xFC040024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * SDRAM Controller (SDRAMC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) *********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* Register read/write macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define MCF_SDRAMC_SDMR 0xFC0B8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define MCF_SDRAMC_SDCR 0xFC0B8004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define MCF_SDRAMC_SDCFG1 0xFC0B8008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define MCF_SDRAMC_SDCFG2 0xFC0B800C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define MCF_SDRAMC_LIMP_FIX 0xFC0B8080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define MCF_SDRAMC_SDDS 0xFC0B8100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define MCF_SDRAMC_SDCS0 0xFC0B8110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define MCF_SDRAMC_SDCS1 0xFC0B8114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define MCF_SDRAMC_SDCS2 0xFC0B8118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define MCF_SDRAMC_SDCS3 0xFC0B811C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* Bit definitions and macros for MCF_SDRAMC_SDMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define MCF_SDRAMC_SDMR_CMD (0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* Bit definitions and macros for MCF_SDRAMC_SDCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define MCF_SDRAMC_SDCR_IPALL (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define MCF_SDRAMC_SDCR_IREF (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define MCF_SDRAMC_SDCR_OE_RULE (0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define MCF_SDRAMC_SDCR_REF (0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define MCF_SDRAMC_SDCR_DDR (0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define MCF_SDRAMC_SDCR_CKE (0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define MCF_SDRAMC_SDCR_PS_16 (0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define MCF_SDRAMC_SDCR_PS_32 (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* Device Errata - LIMP mode work around */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define MCF_SDRAMC_REFRESH (0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* Bit definitions and macros for MCF_SDRAMC_SDDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* Bit definitions and macros for MCF_SDRAMC_SDCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * Edge Port Module (EPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define MCFEPORT_EPPAR (0xFC094000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define MCFEPORT_EPDDR (0xFC094002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define MCFEPORT_EPIER (0xFC094003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define MCFEPORT_EPDR (0xFC094004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define MCFEPORT_EPPDR (0xFC094005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define MCFEPORT_EPFR (0xFC094006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * I2C Module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define MCFI2C_BASE0 (0xFc058000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define MCFI2C_SIZE0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #endif /* m53xxsim_h */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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