^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * m53xxacr.h -- ColdFire version 3 core cache support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef m53xxacr_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define m53xxacr_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * All varients of the ColdFire using version 3 cores have a similar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * cache setup. They have a unified instruction and data cache, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * configurable write-through or copy-back operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Define the Cache Control register flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CACR_EC 0x80000000 /* Enable cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CACR_ESB 0x20000000 /* Enable store buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CACR_DPI 0x10000000 /* Disable invalidation by CPUSHL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CACR_HLCK 0x08000000 /* Half cache lock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CACR_CINVA 0x01000000 /* Invalidate cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CACR_DNFB 0x00000400 /* Inhibited fill buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CACR_DCM_WT 0x00000000 /* Cacheable write-through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CACR_DCM_PRE 0x00000200 /* Cache inhibited, precise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CACR_DCM_IMPRE 0x00000300 /* Cache inhibited, imprecise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CACR_WPROTECT 0x00000020 /* Write protect*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CACR_EUSP 0x00000010 /* Eanble separate user a7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Define the Access Control register flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ACR_ENABLE 0x00008000 /* Enable this ACR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ACR_USER 0x00000000 /* Allow only user accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ACR_SUPER 0x00002000 /* Allow supervisor access only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ACR_ANY 0x00004000 /* Allow any access type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ACR_CM_WT 0x00000000 /* Cacheable, write-through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ACR_CM_PRE 0x00000040 /* Cache inhibited, precise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ACR_WPROTECT 0x00000004 /* Write protect region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Define the cache type and arrangement (needed for pushes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #if defined(CONFIG_M5307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CACHE_SIZE 0x2000 /* 8k of unified cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ICACHE_SIZE CACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DCACHE_SIZE CACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #elif defined(CONFIG_M53xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CACHE_SIZE 0x4000 /* 16k of unified cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ICACHE_SIZE CACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DCACHE_SIZE CACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CACHE_LINE_SIZE 16 /* 16 byte line size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CACHE_WAYS 4 /* 4 ways - set associative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Set the cache controller settings we will use. This default in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * CACR is cache inhibited, we use the ACR register to set cacheing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * enabled on the regions we want (eg RAM).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #if defined(CONFIG_CACHE_COPYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CACHE_TYPE ACR_CM_CB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CACHE_PUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CACHE_TYPE ACR_CM_WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #ifdef CONFIG_COLDFIRE_SW_A7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Unified cache means we will never need to flush for coherency of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * instruction fetch. We will need to flush to maintain memory/DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * coherency though in all cases. And for copyback caches we will need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * to push cached data as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CACHE_INIT (CACHE_MODE + CACR_CINVA - CACR_EC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CACHE_INVALIDATE (CACHE_MODE + CACR_CINVA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CACHE_INVALIDATED (CACHE_MODE + CACR_CINVA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (0x000f0000) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (ACR_ENABLE + ACR_ANY + CACHE_TYPE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ACR1_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif /* m53xxsim_h */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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