^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * m52xxacr.h -- ColdFire version 2 core cache support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef m52xxacr_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define m52xxacr_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * All varients of the ColdFire using version 2 cores have a similar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * cache setup. Although not absolutely identical the cache register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * definitions are compatible for all of them. Mostly they support a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * configurable cache memory that can be instruction only, data only,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * or split instruction and data. The exception is the very old version 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * core based parts, like the 5206(e), 5249 and 5272, which are instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * cache only. Cache size varies from 2k up to 16k.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Define the Cache Control register flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CACR_CENB 0x80000000 /* Enable cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CACR_CFRZ 0x08000000 /* Cache freeze mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CACR_CINV 0x01000000 /* Invalidate cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CACR_DISI 0x00800000 /* Disable instruction cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CACR_DISD 0x00400000 /* Disable data cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CACR_INVI 0x00200000 /* Invalidate instruction cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CACR_INVD 0x00100000 /* Invalidate data cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CACR_DCM 0x00000200 /* Default cache mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CACR_DBWE 0x00000100 /* Buffered write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CACR_DWP 0x00000020 /* Write protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CACR_EUSP 0x00000010 /* Enable separate user a7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Define the Access Control register flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ACR_ENABLE 0x00008000 /* Enable this ACR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ACR_USER 0x00000000 /* Allow only user accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ACR_SUPER 0x00002000 /* Allow supervisor access only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ACR_ANY 0x00004000 /* Allow any access type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ACR_CENB 0x00000000 /* Caching of region enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ACR_CDIS 0x00000040 /* Caching of region disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ACR_BWE 0x00000020 /* Write buffer enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ACR_WPROTECT 0x00000004 /* Write protect region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Set the cache controller settings we will use. On the cores that support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * a split cache configuration we allow all the combinations at Kconfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * time. For those cores that only have an instruction cache we just set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * that as on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #if defined(CONFIG_CACHE_I)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CACHE_TYPE (CACR_DISD + CACR_EUSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CACHE_INVTYPEI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #elif defined(CONFIG_CACHE_D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CACHE_TYPE (CACR_DISI + CACR_EUSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CACHE_INVTYPED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #elif defined(CONFIG_CACHE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CACHE_TYPE CACR_EUSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CACHE_INVTYPEI CACR_INVI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CACHE_INVTYPED CACR_INVD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* This is the instruction cache only devices (no split cache, no eusp) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CACHE_TYPE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CACHE_INVTYPEI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CACHE_INIT (CACR_CINV + CACHE_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #if defined(CACHE_INVTYPEI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #if defined(CACHE_INVTYPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) (0x000f0000) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ACR1_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif /* m52xxsim_h */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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