Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	m528xsim.h -- ColdFire 5280/5282 System Integration Module support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	(C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef	m528xsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define	m528xsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define	CPU_NAME		"COLDFIRE(m528x)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define	CPU_INSTR_PER_JIFFY	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define	MCF_BUSCLK		MCF_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/m52xxacr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *	Define the 5280/5282 SIM register set addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define	MCFICM_INTC0		(MCF_IPSBAR + 0x0c00)	/* Base for Interrupt Ctrl 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define	MCFICM_INTC1		(MCF_IPSBAR + 0x0d00)	/* Base for Interrupt Ctrl 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define	MCFINTC_IMRL		0x0c		/* Interrupt mask 1-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define	MCFINTC_INTFRCH		0x10		/* Interrupt force 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define	MCFINTC_INTFRCL		0x14		/* Interrupt force 1-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define	MCFINTC_IRLR		0x18		/* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define	MCFINTC_IACKL		0x19		/* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define	MCFINTC_ICR0		0x40		/* Base ICR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define	MCFINT_VECBASE		64		/* Vector base number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define	MCFINT_UART0		13		/* Interrupt number for UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	MCFINT_UART1		14		/* Interrupt number for UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define	MCFINT_UART2		15		/* Interrupt number for UART2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define	MCFINT_I2C0		17		/* Interrupt number for I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define	MCFINT_QSPI		18		/* Interrupt number for QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define	MCFINT_FECRX0		23		/* Interrupt number for FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define	MCFINT_FECTX0		27		/* Interrupt number for FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define	MCFINT_FECENTC0		29		/* Interrupt number for FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define	MCFINT_PIT1		55		/* Interrupt number for PIT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define	MCF_IRQ_UART0	        (MCFINT_VECBASE + MCFINT_UART0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define	MCF_IRQ_UART1	        (MCFINT_VECBASE + MCFINT_UART1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define	MCF_IRQ_UART2	        (MCFINT_VECBASE + MCFINT_UART2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define	MCF_IRQ_FECRX0		(MCFINT_VECBASE + MCFINT_FECRX0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define	MCF_IRQ_FECTX0		(MCFINT_VECBASE + MCFINT_FECTX0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define	MCF_IRQ_FECENTC0	(MCFINT_VECBASE + MCFINT_FECENTC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define	MCF_IRQ_QSPI		(MCFINT_VECBASE + MCFINT_QSPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MCF_IRQ_PIT1		(MCFINT_VECBASE + MCFINT_PIT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define	MCF_IRQ_I2C0		(MCFINT_VECBASE + MCFINT_I2C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *	SDRAM configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define	MCFSIM_DCR		(MCF_IPSBAR + 0x00000044) /* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define	MCFSIM_DACR0		(MCF_IPSBAR + 0x00000048) /* Base address 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define	MCFSIM_DMR0		(MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define	MCFSIM_DACR1		(MCF_IPSBAR + 0x00000050) /* Base address 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define	MCFSIM_DMR1		(MCF_IPSBAR + 0x00000054) /* Address mask 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *	DMA unit base addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define	MCFDMA_BASE0		(MCF_IPSBAR + 0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define	MCFDMA_BASE1		(MCF_IPSBAR + 0x00000140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define	MCFDMA_BASE2		(MCF_IPSBAR + 0x00000180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define	MCFDMA_BASE3		(MCF_IPSBAR + 0x000001C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  *	UART module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define	MCFUART_BASE0		(MCF_IPSBAR + 0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define	MCFUART_BASE1		(MCF_IPSBAR + 0x00000240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define	MCFUART_BASE2		(MCF_IPSBAR + 0x00000280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  *	FEC ethernet module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define	MCFFEC_BASE0		(MCF_IPSBAR + 0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define	MCFFEC_SIZE0		0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  *	QSPI module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define	MCFQSPI_BASE		(MCF_IPSBAR + 0x340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define	MCFQSPI_SIZE		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define	MCFQSPI_CS0		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define	MCFQSPI_CS1		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define	MCFQSPI_CS2		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define	MCFQSPI_CS3		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * 	GPIO registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MCFGPIO_PODR_A		(MCF_IPSBAR + 0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MCFGPIO_PODR_B		(MCF_IPSBAR + 0x00100001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MCFGPIO_PODR_C		(MCF_IPSBAR + 0x00100002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCFGPIO_PODR_D		(MCF_IPSBAR + 0x00100003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MCFGPIO_PODR_E		(MCF_IPSBAR + 0x00100004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MCFGPIO_PODR_F		(MCF_IPSBAR + 0x00100005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MCFGPIO_PODR_G		(MCF_IPSBAR + 0x00100006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MCFGPIO_PODR_H		(MCF_IPSBAR + 0x00100007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MCFGPIO_PODR_J		(MCF_IPSBAR + 0x00100008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MCFGPIO_PODR_DD		(MCF_IPSBAR + 0x00100009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCFGPIO_PODR_EH		(MCF_IPSBAR + 0x0010000A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MCFGPIO_PODR_EL		(MCF_IPSBAR + 0x0010000B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MCFGPIO_PODR_AS		(MCF_IPSBAR + 0x0010000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MCFGPIO_PODR_QS		(MCF_IPSBAR + 0x0010000D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MCFGPIO_PODR_SD		(MCF_IPSBAR + 0x0010000E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MCFGPIO_PODR_TC		(MCF_IPSBAR + 0x0010000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MCFGPIO_PODR_TD		(MCF_IPSBAR + 0x00100010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MCFGPIO_PODR_UA		(MCF_IPSBAR + 0x00100011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MCFGPIO_PDDR_A		(MCF_IPSBAR + 0x00100014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MCFGPIO_PDDR_B		(MCF_IPSBAR + 0x00100015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MCFGPIO_PDDR_C		(MCF_IPSBAR + 0x00100016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MCFGPIO_PDDR_D		(MCF_IPSBAR + 0x00100017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MCFGPIO_PDDR_E		(MCF_IPSBAR + 0x00100018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MCFGPIO_PDDR_F		(MCF_IPSBAR + 0x00100019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MCFGPIO_PDDR_G		(MCF_IPSBAR + 0x0010001A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MCFGPIO_PDDR_H		(MCF_IPSBAR + 0x0010001B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MCFGPIO_PDDR_J		(MCF_IPSBAR + 0x0010001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MCFGPIO_PDDR_DD		(MCF_IPSBAR + 0x0010001D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MCFGPIO_PDDR_EH		(MCF_IPSBAR + 0x0010001E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCFGPIO_PDDR_EL		(MCF_IPSBAR + 0x0010001F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MCFGPIO_PDDR_AS		(MCF_IPSBAR + 0x00100020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MCFGPIO_PDDR_QS		(MCF_IPSBAR + 0x00100021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MCFGPIO_PDDR_SD		(MCF_IPSBAR + 0x00100022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MCFGPIO_PDDR_TC		(MCF_IPSBAR + 0x00100023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MCFGPIO_PDDR_TD		(MCF_IPSBAR + 0x00100024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MCFGPIO_PDDR_UA		(MCF_IPSBAR + 0x00100025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MCFGPIO_PPDSDR_A	(MCF_IPSBAR + 0x00100028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MCFGPIO_PPDSDR_B	(MCF_IPSBAR + 0x00100029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MCFGPIO_PPDSDR_C	(MCF_IPSBAR + 0x0010002A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MCFGPIO_PPDSDR_D	(MCF_IPSBAR + 0x0010002B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MCFGPIO_PPDSDR_E	(MCF_IPSBAR + 0x0010002C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MCFGPIO_PPDSDR_F	(MCF_IPSBAR + 0x0010002D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MCFGPIO_PPDSDR_G	(MCF_IPSBAR + 0x0010002E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MCFGPIO_PPDSDR_H	(MCF_IPSBAR + 0x0010002F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MCFGPIO_PPDSDR_J	(MCF_IPSBAR + 0x00100030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MCFGPIO_PPDSDR_DD	(MCF_IPSBAR + 0x00100031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MCFGPIO_PPDSDR_EH	(MCF_IPSBAR + 0x00100032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MCFGPIO_PPDSDR_EL	(MCF_IPSBAR + 0x00100033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MCFGPIO_PPDSDR_AS	(MCF_IPSBAR + 0x00100034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MCFGPIO_PPDSDR_QS	(MCF_IPSBAR + 0x00100035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MCFGPIO_PPDSDR_SD	(MCF_IPSBAR + 0x00100036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MCFGPIO_PPDSDR_TC	(MCF_IPSBAR + 0x00100037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MCFGPIO_PPDSDR_TD	(MCF_IPSBAR + 0x00100038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MCFGPIO_PPDSDR_UA	(MCF_IPSBAR + 0x00100039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MCFGPIO_PCLRR_A		(MCF_IPSBAR + 0x0010003C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MCFGPIO_PCLRR_B		(MCF_IPSBAR + 0x0010003D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MCFGPIO_PCLRR_C		(MCF_IPSBAR + 0x0010003E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MCFGPIO_PCLRR_D		(MCF_IPSBAR + 0x0010003F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MCFGPIO_PCLRR_E		(MCF_IPSBAR + 0x00100040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MCFGPIO_PCLRR_F		(MCF_IPSBAR + 0x00100041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MCFGPIO_PCLRR_G		(MCF_IPSBAR + 0x00100042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MCFGPIO_PCLRR_H		(MCF_IPSBAR + 0x00100043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MCFGPIO_PCLRR_J		(MCF_IPSBAR + 0x00100044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MCFGPIO_PCLRR_DD	(MCF_IPSBAR + 0x00100045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MCFGPIO_PCLRR_EH	(MCF_IPSBAR + 0x00100046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MCFGPIO_PCLRR_EL	(MCF_IPSBAR + 0x00100047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MCFGPIO_PCLRR_AS	(MCF_IPSBAR + 0x00100048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MCFGPIO_PCLRR_QS	(MCF_IPSBAR + 0x00100049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MCFGPIO_PCLRR_SD	(MCF_IPSBAR + 0x0010004A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MCFGPIO_PCLRR_TC	(MCF_IPSBAR + 0x0010004B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MCFGPIO_PCLRR_TD	(MCF_IPSBAR + 0x0010004C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MCFGPIO_PCLRR_UA	(MCF_IPSBAR + 0x0010004D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MCFGPIO_PBCDPAR		(MCF_IPSBAR + 0x00100050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MCFGPIO_PFPAR		(MCF_IPSBAR + 0x00100051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MCFGPIO_PEPAR		(MCF_IPSBAR + 0x00100052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MCFGPIO_PJPAR		(MCF_IPSBAR + 0x00100054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MCFGPIO_PSDPAR		(MCF_IPSBAR + 0x00100055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MCFGPIO_PASPAR		(MCF_IPSBAR + 0x00100056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MCFGPIO_PEHLPAR		(MCF_IPSBAR + 0x00100058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MCFGPIO_PQSPAR		(MCF_IPSBAR + 0x00100059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MCFGPIO_PTCPAR		(MCF_IPSBAR + 0x0010005A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MCFGPIO_PTDPAR		(MCF_IPSBAR + 0x0010005B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MCFGPIO_PUAPAR		(MCF_IPSBAR + 0x0010005C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * PIT timer base addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define	MCFPIT_BASE1		(MCF_IPSBAR + 0x00150000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define	MCFPIT_BASE2		(MCF_IPSBAR + 0x00160000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define	MCFPIT_BASE3		(MCF_IPSBAR + 0x00170000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define	MCFPIT_BASE4		(MCF_IPSBAR + 0x00180000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * 	Edge Port registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MCFEPORT_EPPAR		(MCF_IPSBAR + 0x00130000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MCFEPORT_EPDDR		(MCF_IPSBAR + 0x00130002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MCFEPORT_EPIER		(MCF_IPSBAR + 0x00130003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MCFEPORT_EPDR		(MCF_IPSBAR + 0x00130004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MCFEPORT_EPPDR		(MCF_IPSBAR + 0x00130005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MCFEPORT_EPFR		(MCF_IPSBAR + 0x00130006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  * 	Queued ADC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MCFQADC_PORTQA		(MCF_IPSBAR + 0x00190006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MCFQADC_PORTQB		(MCF_IPSBAR + 0x00190007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MCFQADC_DDRQA		(MCF_IPSBAR + 0x00190008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MCFQADC_DDRQB		(MCF_IPSBAR + 0x00190009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  * 	General Purpose Timers registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MCFGPTA_GPTPORT		(MCF_IPSBAR + 0x001A001D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MCFGPTA_GPTDDR		(MCF_IPSBAR + 0x001A001E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MCFGPTB_GPTPORT		(MCF_IPSBAR + 0x001B001D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MCFGPTB_GPTDDR		(MCF_IPSBAR + 0x001B001E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * definitions for generic gpio support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MCFGPIO_PODR		MCFGPIO_PODR_A	/* port output data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MCFGPIO_PDDR		MCFGPIO_PDDR_A	/* port data direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MCFGPIO_PPDR		MCFGPIO_PPDSDR_A/* port pin data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MCFGPIO_SETR		MCFGPIO_PPDSDR_A/* set output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MCFGPIO_CLRR		MCFGPIO_PCLRR_A	/* clr output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MCFGPIO_IRQ_MAX		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MCFGPIO_IRQ_VECBASE	MCFINT_VECBASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MCFGPIO_PIN_MAX		180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  *  Reset Control Unit (relative to IPSBAR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define	MCF_RCR			(MCF_IPSBAR + 0x110000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define	MCF_RSR			(MCF_IPSBAR + 0x110001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  * I2C module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define	MCFI2C_BASE0		(MCF_IPSBAR + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define	MCFI2C_SIZE0		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #endif	/* m528xsim_h */