^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * m5272sim.h -- ColdFire 5272 System Integration Module support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef m5272sim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define m5272sim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CPU_NAME "COLDFIRE(m5272)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CPU_INSTR_PER_JIFFY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MCF_BUSCLK MCF_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/m52xxacr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Define the 5272 SIM register set addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MCFFEC_SIZE0 0x1d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Define system peripheral IRQ usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MCFINT_VECBASE 64 /* Base of interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MCF_IRQ_SPURIOUS 64 /* User Spurious */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MCF_IRQ_EINT2 66 /* External Interrupt 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MCF_IRQ_EINT3 67 /* External Interrupt 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MCF_IRQ_EINT4 68 /* External Interrupt 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MCF_IRQ_TIMER1 69 /* Timer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MCF_IRQ_TIMER2 70 /* Timer 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MCF_IRQ_TIMER3 71 /* Timer 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCF_IRQ_TIMER4 72 /* Timer 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MCF_IRQ_UART0 73 /* UART 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MCF_IRQ_UART1 74 /* UART 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MCF_IRQ_USB0 77 /* USB Endpoint 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MCF_IRQ_USB1 78 /* USB Endpoint 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCF_IRQ_USB2 79 /* USB Endpoint 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MCF_IRQ_USB3 80 /* USB Endpoint 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MCF_IRQ_USB4 81 /* USB Endpoint 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MCF_IRQ_USB5 82 /* USB Endpoint 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MCF_IRQ_USB6 83 /* USB Endpoint 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MCF_IRQ_USB7 84 /* USB Endpoint 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MCF_IRQ_DMA 85 /* DMA Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MCF_IRQ_QSPI 89 /* Queued Serial Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MCF_IRQ_EINT5 90 /* External Interrupt 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MCF_IRQ_EINT6 91 /* External Interrupt 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MCF_IRQ_SWTO 92 /* Software Watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MCFINT_VECMAX 95 /* Maxmum interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MCF_IRQ_TIMER MCF_IRQ_TIMER1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MCF_IRQ_PROFILER MCF_IRQ_TIMER2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Generic GPIO support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MCFGPIO_PIN_MAX 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MCFGPIO_IRQ_MAX -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MCFGPIO_IRQ_VECBASE -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif /* m5272sim_h */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags