Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	m525xsim.h -- ColdFire 525x System Integration Module support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	(C) Copyright 2012, Steven king <sfking@fdwdc.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	(C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #ifndef	m525xsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define m525xsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *	This header supports ColdFire 5249, 5251 and 5253. There are a few
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *	little differences between them, but most of the peripheral support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *	can be used by all of them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CPU_NAME		"COLDFIRE(m525x)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CPU_INSTR_PER_JIFFY	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MCF_BUSCLK		(MCF_CLK / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/m52xxacr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *	The 525x has a second MBAR region, define its address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MCF_MBAR2		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *	Define the 525x SIM register set addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MCFSIM_RSR		(MCF_MBAR + 0x00)	/* Reset Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog srv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MCFSIM_MPARK		(MCF_MBAR + 0x0C)	/* BUS Master Ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MCFSIM_IPR		(MCF_MBAR + 0x40)	/* Interrupt Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MCFSIM_IMR		(MCF_MBAR + 0x44)	/* Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MCFSIM_ICR0		(MCF_MBAR + 0x4c)	/* Intr Ctrl reg 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MCFSIM_ICR1		(MCF_MBAR + 0x4d)	/* Intr Ctrl reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MCFSIM_ICR2		(MCF_MBAR + 0x4e)	/* Intr Ctrl reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MCFSIM_ICR3		(MCF_MBAR + 0x4f)	/* Intr Ctrl reg 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MCFSIM_ICR4		(MCF_MBAR + 0x50)	/* Intr Ctrl reg 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MCFSIM_ICR5		(MCF_MBAR + 0x51)	/* Intr Ctrl reg 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MCFSIM_ICR6		(MCF_MBAR + 0x52)	/* Intr Ctrl reg 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MCFSIM_ICR7		(MCF_MBAR + 0x53)	/* Intr Ctrl reg 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MCFSIM_ICR8		(MCF_MBAR + 0x54)	/* Intr Ctrl reg 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MCFSIM_ICR9		(MCF_MBAR + 0x55)	/* Intr Ctrl reg 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MCFSIM_ICR10		(MCF_MBAR + 0x56)	/* Intr Ctrl reg 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MCFSIM_ICR11		(MCF_MBAR + 0x57)	/* Intr Ctrl reg 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MCFSIM_CSAR0		(MCF_MBAR + 0x80)	/* CS 0 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MCFSIM_CSMR0		(MCF_MBAR + 0x84)	/* CS 0 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MCFSIM_CSCR0		(MCF_MBAR + 0x8a)	/* CS 0 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MCFSIM_CSAR1		(MCF_MBAR + 0x8c)	/* CS 1 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MCFSIM_CSMR1		(MCF_MBAR + 0x90)	/* CS 1 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MCFSIM_CSCR1		(MCF_MBAR + 0x96)	/* CS 1 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MCFSIM_CSAR2		(MCF_MBAR + 0x98)	/* CS 2 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MCFSIM_CSMR2		(MCF_MBAR + 0x9c)	/* CS 2 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MCFSIM_CSCR2		(MCF_MBAR + 0xa2)	/* CS 2 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MCFSIM_CSAR3		(MCF_MBAR + 0xa4)	/* CS 3 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MCFSIM_CSMR3		(MCF_MBAR + 0xa8)	/* CS 3 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MCFSIM_CSCR3		(MCF_MBAR + 0xae)	/* CS 3 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MCFSIM_CSAR4		(MCF_MBAR + 0xb0)	/* CS 4 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MCFSIM_CSMR4		(MCF_MBAR + 0xb4)	/* CS 4 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MCFSIM_CSCR4		(MCF_MBAR + 0xba)	/* CS 4 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MCFSIM_DACR0		(MCF_MBAR + 0x108)	/* DRAM 0 Addr/Ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MCFSIM_DMR0		(MCF_MBAR + 0x10c)	/* DRAM 0 Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MCFSIM_DACR1		(MCF_MBAR + 0x110)	/* DRAM 1 Addr/Ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MCFSIM_DMR1		(MCF_MBAR + 0x114)	/* DRAM 1 Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * Secondary Interrupt Controller (in MBAR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MCFINTC2_INTBASE	(MCF_MBAR2 + 0x168)	/* Base Vector Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MCFINTC2_INTPRI1	(MCF_MBAR2 + 0x140)	/* 0-7 priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MCFINTC2_INTPRI2	(MCF_MBAR2 + 0x144)	/* 8-15 priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MCFINTC2_INTPRI3	(MCF_MBAR2 + 0x148)	/* 16-23 priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define MCFINTC2_INTPRI4	(MCF_MBAR2 + 0x14c)	/* 24-31 priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define MCFINTC2_INTPRI5	(MCF_MBAR2 + 0x150)	/* 32-39 priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MCFINTC2_INTPRI6	(MCF_MBAR2 + 0x154)	/* 40-47 priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MCFINTC2_INTPRI7	(MCF_MBAR2 + 0x158)	/* 48-55 priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MCFINTC2_INTPRI8	(MCF_MBAR2 + 0x15c)	/* 56-63 priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MCFINTC2_INTPRI_REG(i)	(MCFINTC2_INTPRI1 + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				((((i) - MCFINTC2_VECBASE) / 8) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define MCFINTC2_INTPRI_BITS(b, i)	((b) << (((i) % 8) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  *	Timer module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define MCFTIMER_BASE1		(MCF_MBAR + 0x140)	/* Base of TIMER1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MCFTIMER_BASE2		(MCF_MBAR + 0x180)	/* Base of TIMER2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  *	UART module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MCFUART_BASE0		(MCF_MBAR + 0x1c0)	/* Base address UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MCFUART_BASE1		(MCF_MBAR + 0x200)	/* Base address UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  *	QSPI module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MCFQSPI_BASE		(MCF_MBAR + 0x400)	/* Base address QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MCFQSPI_SIZE		0x40			/* Register set size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifdef CONFIG_M5249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MCFQSPI_CS0		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCFQSPI_CS1		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MCFQSPI_CS2		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MCFQSPI_CS3		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MCFQSPI_CS0		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MCFQSPI_CS1		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MCFQSPI_CS2		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MCFQSPI_CS3		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  *	I2C module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MCFI2C_BASE0		(MCF_MBAR + 0x280)	/* Base address I2C0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MCFI2C_SIZE0		0x20			/* Register set size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MCFI2C_BASE1		(MCF_MBAR2 + 0x440)	/* Base address I2C1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MCFI2C_SIZE1		0x20			/* Register set size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  *	DMA unit base addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MCFDMA_BASE0		(MCF_MBAR + 0x300)	/* Base address DMA 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MCFDMA_BASE1		(MCF_MBAR + 0x340)	/* Base address DMA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MCFDMA_BASE2		(MCF_MBAR + 0x380)	/* Base address DMA 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  *	Some symbol defines for the above...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MCFSIM_SWDICR		MCFSIM_ICR0	/* Watchdog timer ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MCFSIM_TIMER2ICR	MCFSIM_ICR2	/* Timer 2 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MCFSIM_I2CICR		MCFSIM_ICR3	/* I2C ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MCFSIM_UART1ICR		MCFSIM_ICR4	/* UART 1 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MCFSIM_UART2ICR		MCFSIM_ICR5	/* UART 2 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MCFSIM_DMA0ICR		MCFSIM_ICR6	/* DMA 0 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MCFSIM_DMA1ICR		MCFSIM_ICR7	/* DMA 1 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MCFSIM_DMA2ICR		MCFSIM_ICR8	/* DMA 2 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MCFSIM_DMA3ICR		MCFSIM_ICR9	/* DMA 3 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MCFSIM_QSPIICR		MCFSIM_ICR10	/* QSPI ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  *	Define system peripheral IRQ usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MCF_IRQ_QSPI		28		/* QSPI, Level 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MCF_IRQ_I2C0		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MCF_IRQ_TIMER		30		/* Timer0, Level 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MCF_IRQ_PROFILER	31		/* Timer1, Level 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MCF_IRQ_UART0		73		/* UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MCF_IRQ_UART1		74		/* UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * Define the base interrupt for the second interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  * We set it to 128, out of the way of the base interrupts, and plenty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * of room for its 64 interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MCFINTC2_VECBASE	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MCF_IRQ_GPIO0		(MCFINTC2_VECBASE + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MCF_IRQ_GPIO1		(MCFINTC2_VECBASE + 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MCF_IRQ_GPIO2		(MCFINTC2_VECBASE + 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MCF_IRQ_GPIO3		(MCFINTC2_VECBASE + 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MCF_IRQ_GPIO4		(MCFINTC2_VECBASE + 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MCF_IRQ_GPIO5		(MCFINTC2_VECBASE + 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MCF_IRQ_GPIO6		(MCFINTC2_VECBASE + 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MCF_IRQ_GPIO7		(MCFINTC2_VECBASE + 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MCF_IRQ_USBWUP		(MCFINTC2_VECBASE + 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MCF_IRQ_I2C1		(MCFINTC2_VECBASE + 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  *	General purpose IO registers (in MBAR2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MCFSIM2_GPIOREAD	(MCF_MBAR2 + 0x000)	/* GPIO read values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MCFSIM2_GPIOWRITE	(MCF_MBAR2 + 0x004)	/* GPIO write values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MCFSIM2_GPIOENABLE	(MCF_MBAR2 + 0x008)	/* GPIO enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MCFSIM2_GPIOFUNC	(MCF_MBAR2 + 0x00C)	/* GPIO function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MCFSIM2_GPIO1READ	(MCF_MBAR2 + 0x0B0)	/* GPIO1 read values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MCFSIM2_GPIO1WRITE	(MCF_MBAR2 + 0x0B4)	/* GPIO1 write values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MCFSIM2_GPIO1ENABLE	(MCF_MBAR2 + 0x0B8)	/* GPIO1 enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MCFSIM2_GPIO1FUNC	(MCF_MBAR2 + 0x0BC)	/* GPIO1 function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MCFSIM2_GPIOINTSTAT	(MCF_MBAR2 + 0xc0)	/* GPIO intr status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MCFSIM2_GPIOINTCLEAR	(MCF_MBAR2 + 0xc0)	/* GPIO intr clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MCFSIM2_GPIOINTENABLE	(MCF_MBAR2 + 0xc4)	/* GPIO intr enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MCFSIM2_DMAROUTE	(MCF_MBAR2 + 0x188)     /* DMA routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MCFSIM2_IDECONFIG1	(MCF_MBAR2 + 0x18c)	/* IDEconfig1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MCFSIM2_IDECONFIG2	(MCF_MBAR2 + 0x190)	/* IDEconfig2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * Generic GPIO support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MCFGPIO_PIN_MAX		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #ifdef CONFIG_M5249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MCFGPIO_IRQ_MAX		-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MCFGPIO_IRQ_VECBASE	-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MCFGPIO_IRQ_MAX		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MCFGPIO_IRQ_VECBASE	MCF_IRQ_GPIO0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #ifdef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #ifdef CONFIG_M5249C3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  *	The M5249C3 board needs a little help getting all its SIM devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  *	initialized at kernel start time. dBUG doesn't set much up, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  *	we need to do it manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .macro m5249c3_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 *	Set MBAR1 and MBAR2, just incase they are not set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	movel	#0x10000001,%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	movec	%a0,%MBAR			/* map MBAR region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	subql	#1,%a0				/* get MBAR address in a0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	movel	#0x80000001,%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	movec	%a1,#3086			/* map MBAR2 region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	subql	#1,%a1				/* get MBAR2 address in a1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 *      Move secondary interrupts to their base (128).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	moveb	#MCFINTC2_VECBASE,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	moveb	%d0,0x16b(%a1)			/* interrupt base register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 *      Work around broken CSMR0/DRAM vector problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	movel	#0x001F0021,%d0			/* disable C/I bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	movel	%d0,0x84(%a0)			/* set CSMR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	 *	Disable the PLL firstly. (Who knows what state it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	 *	in here!).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	movel	0x180(%a1),%d0			/* get current PLL value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	andl	#0xfffffffe,%d0			/* PLL bypass first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	movel	%d0,0x180(%a1)			/* set PLL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #if CONFIG_CLOCK_FREQ == 140000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	 *	Set initial clock frequency. This assumes M5249C3 board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 *	is fitted with 11.2896MHz crystal. It will program the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	 *	PLL for 140MHz. Lets go fast :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	movel	#0x125a40f0,%d0			/* set for 140MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	movel	%d0,0x180(%a1)			/* set PLL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	orl	#0x1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	movel	%d0,0x180(%a1)			/* set PLL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	 *	Setup CS1 for ethernet controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	 *	(Setup as per M5249C3 doco).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	movel  #0xe0000000,%d0			/* CS1 mapped at 0xe0000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	movel  %d0,0x8c(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	movel  #0x001f0021,%d0			/* CS1 size of 1Mb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	movel  %d0,0x90(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	movew  #0x0080,%d0			/* CS1 = 16bit port, AA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	movew  %d0,0x96(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	 *	Setup CS2 for IDE interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	movel	#0x50000000,%d0			/* CS2 mapped at 0x50000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	movel	%d0,0x98(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	movel	#0x001f0001,%d0			/* CS2 size of 1MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	movel	%d0,0x9c(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	movew	#0x0080,%d0			/* CS2 = 16bit, TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	movew	%d0,0xa2(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	movel	#0x00107000,%d0			/* IDEconfig1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	movel	%d0,0x18c(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	movel	#0x000c0400,%d0			/* IDEconfig2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	movel	%d0,0x190(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	movel	#0x00080000,%d0			/* GPIO19, IDE reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	orl	%d0,0xc(%a1)			/* function GPIO19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	orl	%d0,0x8(%a1)			/* enable GPIO19 as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)         orl	%d0,0x4(%a1)			/* de-assert IDE reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define	PLATFORM_SETUP	m5249c3_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #endif /* CONFIG_M5249C3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif /* __ASSEMBLER__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #endif	/* m525xsim_h */