Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	m523xsim.h -- ColdFire 523x System Integration Module support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	(C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef	m523xsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define	m523xsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define	CPU_NAME		"COLDFIRE(m523x)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define	CPU_INSTR_PER_JIFFY	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define	MCF_BUSCLK		(MCF_CLK / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/m52xxacr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *	Define the 523x SIM register set addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define	MCFICM_INTC0		(MCF_IPSBAR + 0x0c00)	/* Base for Interrupt Ctrl 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define	MCFICM_INTC1		(MCF_IPSBAR + 0x0d00)	/* Base for Interrupt Ctrl 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define	MCFINTC_IMRL		0x0c		/* Interrupt mask 1-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define	MCFINTC_INTFRCH		0x10		/* Interrupt force 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define	MCFINTC_INTFRCL		0x14		/* Interrupt force 1-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define	MCFINTC_IRLR		0x18		/* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define	MCFINTC_IACKL		0x19		/* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define	MCFINTC_ICR0		0x40		/* Base ICR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define	MCFINT_VECBASE		64		/* Vector base number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define	MCFINT_UART0		13		/* Interrupt number for UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	MCFINT_UART1		14		/* Interrupt number for UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define	MCFINT_UART2		15		/* Interrupt number for UART2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define	MCFINT_I2C0		17		/* Interrupt number for I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define	MCFINT_QSPI		18		/* Interrupt number for QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define	MCFINT_FECRX0		23		/* Interrupt number for FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define	MCFINT_FECTX0		27		/* Interrupt number for FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define	MCFINT_FECENTC0		29		/* Interrupt number for FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define	MCFINT_PIT1		36		/* Interrupt number for PIT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define	MCF_IRQ_UART0	        (MCFINT_VECBASE + MCFINT_UART0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define	MCF_IRQ_UART1	        (MCFINT_VECBASE + MCFINT_UART1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define	MCF_IRQ_UART2	        (MCFINT_VECBASE + MCFINT_UART2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define	MCF_IRQ_FECRX0		(MCFINT_VECBASE + MCFINT_FECRX0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define	MCF_IRQ_FECTX0		(MCFINT_VECBASE + MCFINT_FECTX0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define	MCF_IRQ_FECENTC0	(MCFINT_VECBASE + MCFINT_FECENTC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define	MCF_IRQ_QSPI		(MCFINT_VECBASE + MCFINT_QSPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MCF_IRQ_PIT1		(MCFINT_VECBASE + MCFINT_PIT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define	MCF_IRQ_I2C0		(MCFINT_VECBASE + MCFINT_I2C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *	SDRAM configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define	MCFSIM_DCR		(MCF_IPSBAR + 0x44)	/* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define	MCFSIM_DACR0		(MCF_IPSBAR + 0x48)	/* Base address 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define	MCFSIM_DMR0		(MCF_IPSBAR + 0x4c)	/* Address mask 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define	MCFSIM_DACR1		(MCF_IPSBAR + 0x50)	/* Base address 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define	MCFSIM_DMR1		(MCF_IPSBAR + 0x54)	/* Address mask 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *  Reset Control Unit (relative to IPSBAR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define	MCF_RCR			(MCF_IPSBAR + 0x110000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define	MCF_RSR			(MCF_IPSBAR + 0x110001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  *  UART module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MCFUART_BASE0		(MCF_IPSBAR + 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MCFUART_BASE1		(MCF_IPSBAR + 0x240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MCFUART_BASE2		(MCF_IPSBAR + 0x280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  *  FEC ethernet module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define	MCFFEC_BASE0		(MCF_IPSBAR + 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define	MCFFEC_SIZE0		0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  *  QSPI module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define	MCFQSPI_BASE		(MCF_IPSBAR + 0x340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define	MCFQSPI_SIZE		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define	MCFQSPI_CS0		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define	MCFQSPI_CS1		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define	MCFQSPI_CS2		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define	MCFQSPI_CS3		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  *  GPIO module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MCFGPIO_PODR_ADDR	(MCF_IPSBAR + 0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MCFGPIO_PODR_DATAH	(MCF_IPSBAR + 0x100001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCFGPIO_PODR_DATAL	(MCF_IPSBAR + 0x100002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MCFGPIO_PODR_BUSCTL	(MCF_IPSBAR + 0x100003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MCFGPIO_PODR_BS		(MCF_IPSBAR + 0x100004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MCFGPIO_PODR_CS		(MCF_IPSBAR + 0x100005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MCFGPIO_PODR_SDRAM	(MCF_IPSBAR + 0x100006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MCFGPIO_PODR_FECI2C	(MCF_IPSBAR + 0x100007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MCFGPIO_PODR_UARTH	(MCF_IPSBAR + 0x100008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCFGPIO_PODR_UARTL	(MCF_IPSBAR + 0x100009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MCFGPIO_PODR_QSPI	(MCF_IPSBAR + 0x10000A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MCFGPIO_PODR_TIMER	(MCF_IPSBAR + 0x10000B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MCFGPIO_PODR_ETPU	(MCF_IPSBAR + 0x10000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MCFGPIO_PDDR_ADDR	(MCF_IPSBAR + 0x100010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MCFGPIO_PDDR_DATAH	(MCF_IPSBAR + 0x100011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MCFGPIO_PDDR_DATAL	(MCF_IPSBAR + 0x100012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MCFGPIO_PDDR_BUSCTL	(MCF_IPSBAR + 0x100013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MCFGPIO_PDDR_BS		(MCF_IPSBAR + 0x100014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MCFGPIO_PDDR_CS		(MCF_IPSBAR + 0x100015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MCFGPIO_PDDR_SDRAM	(MCF_IPSBAR + 0x100016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MCFGPIO_PDDR_FECI2C	(MCF_IPSBAR + 0x100017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MCFGPIO_PDDR_UARTH	(MCF_IPSBAR + 0x100018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MCFGPIO_PDDR_UARTL	(MCF_IPSBAR + 0x100019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MCFGPIO_PDDR_QSPI	(MCF_IPSBAR + 0x10001A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MCFGPIO_PDDR_TIMER	(MCF_IPSBAR + 0x10001B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MCFGPIO_PDDR_ETPU	(MCF_IPSBAR + 0x10001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MCFGPIO_PPDSDR_ADDR	(MCF_IPSBAR + 0x100020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCFGPIO_PPDSDR_DATAH	(MCF_IPSBAR + 0x100021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MCFGPIO_PPDSDR_DATAL	(MCF_IPSBAR + 0x100022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MCFGPIO_PPDSDR_BUSCTL	(MCF_IPSBAR + 0x100023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MCFGPIO_PPDSDR_BS	(MCF_IPSBAR + 0x100024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MCFGPIO_PPDSDR_CS	(MCF_IPSBAR + 0x100025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MCFGPIO_PPDSDR_SDRAM	(MCF_IPSBAR + 0x100026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MCFGPIO_PPDSDR_FECI2C	(MCF_IPSBAR + 0x100027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MCFGPIO_PPDSDR_UARTH	(MCF_IPSBAR + 0x100028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MCFGPIO_PPDSDR_UARTL	(MCF_IPSBAR + 0x100029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MCFGPIO_PPDSDR_QSPI	(MCF_IPSBAR + 0x10002A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MCFGPIO_PPDSDR_TIMER	(MCF_IPSBAR + 0x10002B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MCFGPIO_PPDSDR_ETPU	(MCF_IPSBAR + 0x10002C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MCFGPIO_PCLRR_ADDR	(MCF_IPSBAR + 0x100030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MCFGPIO_PCLRR_DATAH	(MCF_IPSBAR + 0x100031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MCFGPIO_PCLRR_DATAL	(MCF_IPSBAR + 0x100032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MCFGPIO_PCLRR_BUSCTL	(MCF_IPSBAR + 0x100033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MCFGPIO_PCLRR_BS	(MCF_IPSBAR + 0x100034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MCFGPIO_PCLRR_CS	(MCF_IPSBAR + 0x100035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MCFGPIO_PCLRR_SDRAM	(MCF_IPSBAR + 0x100036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MCFGPIO_PCLRR_FECI2C	(MCF_IPSBAR + 0x100037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MCFGPIO_PCLRR_UARTH	(MCF_IPSBAR + 0x100038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MCFGPIO_PCLRR_UARTL	(MCF_IPSBAR + 0x100039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MCFGPIO_PCLRR_QSPI	(MCF_IPSBAR + 0x10003A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MCFGPIO_PCLRR_TIMER	(MCF_IPSBAR + 0x10003B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MCFGPIO_PCLRR_ETPU	(MCF_IPSBAR + 0x10003C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * PIT timer base addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define	MCFPIT_BASE1		(MCF_IPSBAR + 0x150000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define	MCFPIT_BASE2		(MCF_IPSBAR + 0x160000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define	MCFPIT_BASE3		(MCF_IPSBAR + 0x170000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define	MCFPIT_BASE4		(MCF_IPSBAR + 0x180000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * EPort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MCFEPORT_EPPAR		(MCF_IPSBAR + 0x130000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MCFEPORT_EPDDR		(MCF_IPSBAR + 0x130002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MCFEPORT_EPIER		(MCF_IPSBAR + 0x130003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MCFEPORT_EPDR		(MCF_IPSBAR + 0x130004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MCFEPORT_EPPDR		(MCF_IPSBAR + 0x130005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MCFEPORT_EPFR		(MCF_IPSBAR + 0x130006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  * Generic GPIO support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MCFGPIO_PODR		MCFGPIO_PODR_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MCFGPIO_PDDR		MCFGPIO_PDDR_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MCFGPIO_PPDR		MCFGPIO_PPDSDR_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MCFGPIO_SETR		MCFGPIO_PPDSDR_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MCFGPIO_CLRR		MCFGPIO_PCLRR_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MCFGPIO_PIN_MAX		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MCFGPIO_IRQ_MAX		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MCFGPIO_IRQ_VECBASE	MCFINT_VECBASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * Pin Assignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define	MCFGPIO_PAR_AD		(MCF_IPSBAR + 0x100040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define	MCFGPIO_PAR_BUSCTL	(MCF_IPSBAR + 0x100042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define	MCFGPIO_PAR_BS		(MCF_IPSBAR + 0x100044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define	MCFGPIO_PAR_CS		(MCF_IPSBAR + 0x100045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define	MCFGPIO_PAR_SDRAM	(MCF_IPSBAR + 0x100046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define	MCFGPIO_PAR_FECI2C	(MCF_IPSBAR + 0x100047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define	MCFGPIO_PAR_UART	(MCF_IPSBAR + 0x100048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define	MCFGPIO_PAR_QSPI	(MCF_IPSBAR + 0x10004A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define	MCFGPIO_PAR_TIMER	(MCF_IPSBAR + 0x10004C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define	MCFGPIO_PAR_ETPU	(MCF_IPSBAR + 0x10004E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * DMA unit base addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define	MCFDMA_BASE0		(MCF_IPSBAR + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define	MCFDMA_BASE1		(MCF_IPSBAR + 0x140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define	MCFDMA_BASE2		(MCF_IPSBAR + 0x180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define	MCFDMA_BASE3		(MCF_IPSBAR + 0x1C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * I2C module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define	MCFI2C_BASE0		(MCF_IPSBAR + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define	MCFI2C_SIZE0		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #endif	/* m523xsim_h */