Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef m520xsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define m520xsim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define	CPU_NAME		"COLDFIRE(m520x)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define	CPU_INSTR_PER_JIFFY	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define	MCF_BUSCLK		(MCF_CLK / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/m52xxacr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *  Define the 520x SIM register set addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MCFICM_INTC0        0xFC048000  /* Base for Interrupt Ctrl 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MCFINTC_IPRH        0x00        /* Interrupt pending 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MCFINTC_IPRL        0x04        /* Interrupt pending 1-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MCFINTC_IMRH        0x08        /* Interrupt mask 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MCFINTC_IMRL        0x0c        /* Interrupt mask 1-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MCFINTC_INTFRCH     0x10        /* Interrupt force 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MCFINTC_INTFRCL     0x14        /* Interrupt force 1-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MCFINTC_SIMR        0x1c        /* Set interrupt mask 0-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MCFINTC_CIMR        0x1d        /* Clear interrupt mask 0-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MCFINTC_ICR0        0x40        /* Base ICR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *  The common interrupt controller code just wants to know the absolute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *  address to the SIMR and CIMR registers (not offsets into IPSBAR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *  The 520x family only has a single INTC unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MCFINTC0_SIMR       (MCFICM_INTC0 + MCFINTC_SIMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MCFINTC0_CIMR       (MCFICM_INTC0 + MCFINTC_CIMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define	MCFINTC0_ICR0       (MCFICM_INTC0 + MCFINTC_ICR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MCFINTC1_SIMR       (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MCFINTC1_CIMR       (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define	MCFINTC1_ICR0       (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MCFINTC2_SIMR       (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MCFINTC2_CIMR       (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MCFINTC2_ICR0       (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MCFINT_VECBASE      64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MCFINT_UART0        26          /* Interrupt number for UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MCFINT_UART1        27          /* Interrupt number for UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MCFINT_UART2        28          /* Interrupt number for UART2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MCFINT_I2C0         30          /* Interrupt number for I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MCFINT_QSPI         31          /* Interrupt number for QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MCFINT_FECRX0	    36		/* Interrupt number for FEC RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MCFINT_FECTX0	    40		/* Interrupt number for FEC RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MCFINT_FECENTC0	    42		/* Interrupt number for FEC RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MCFINT_PIT1         4           /* Interrupt number for PIT1 (PIT0 in processor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MCF_IRQ_UART0	    (MCFINT_VECBASE + MCFINT_UART0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MCF_IRQ_UART1	    (MCFINT_VECBASE + MCFINT_UART1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MCF_IRQ_UART2	    (MCFINT_VECBASE + MCFINT_UART2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MCF_IRQ_FECRX0	    (MCFINT_VECBASE + MCFINT_FECRX0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MCF_IRQ_FECTX0	    (MCFINT_VECBASE + MCFINT_FECTX0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MCF_IRQ_FECENTC0    (MCFINT_VECBASE + MCFINT_FECENTC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define	MCF_IRQ_QSPI	    (MCFINT_VECBASE + MCFINT_QSPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MCF_IRQ_PIT1        (MCFINT_VECBASE + MCFINT_PIT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MCF_IRQ_I2C0        (MCFINT_VECBASE + MCFINT_I2C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  *  SDRAM configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define MCFSIM_SDMR         0xFC0a8000	/* SDRAM Mode/Extended Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MCFSIM_SDCR         0xFC0a8004	/* SDRAM Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MCFSIM_SDCFG1       0xFC0a8008	/* SDRAM Configuration Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MCFSIM_SDCFG2       0xFC0a800c	/* SDRAM Configuration Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MCFSIM_SDCS0        0xFC0a8110	/* SDRAM Chip Select 0 Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MCFSIM_SDCS1        0xFC0a8114	/* SDRAM Chip Select 1 Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * EPORT and GPIO registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MCFEPORT_EPPAR			0xFC088000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MCFEPORT_EPDDR			0xFC088002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MCFEPORT_EPIER			0xFC088003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define MCFEPORT_EPDR			0xFC088004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MCFEPORT_EPPDR			0xFC088005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define MCFEPORT_EPFR			0xFC088006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define MCFGPIO_PODR_BUSCTL		0xFC0A4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MCFGPIO_PODR_BE			0xFC0A4001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MCFGPIO_PODR_CS			0xFC0A4002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define MCFGPIO_PODR_FECI2C		0xFC0A4003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define MCFGPIO_PODR_QSPI		0xFC0A4004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MCFGPIO_PODR_TIMER		0xFC0A4005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define MCFGPIO_PODR_UART		0xFC0A4006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MCFGPIO_PODR_FECH		0xFC0A4007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MCFGPIO_PODR_FECL		0xFC0A4008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MCFGPIO_PDDR_BUSCTL		0xFC0A400C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MCFGPIO_PDDR_BE			0xFC0A400D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MCFGPIO_PDDR_CS			0xFC0A400E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MCFGPIO_PDDR_FECI2C		0xFC0A400F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCFGPIO_PDDR_QSPI		0xFC0A4010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MCFGPIO_PDDR_TIMER		0xFC0A4011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MCFGPIO_PDDR_UART		0xFC0A4012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MCFGPIO_PDDR_FECH		0xFC0A4013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MCFGPIO_PDDR_FECL		0xFC0A4014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MCFGPIO_PPDSDR_CS		0xFC0A401A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCFGPIO_PPDSDR_FECI2C		0xFC0A401B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MCFGPIO_PPDSDR_QSPI		0xFC0A401C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MCFGPIO_PPDSDR_TIMER		0xFC0A401D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MCFGPIO_PPDSDR_UART		0xFC0A401E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MCFGPIO_PPDSDR_FECH		0xFC0A401F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MCFGPIO_PPDSDR_FECL		0xFC0A4020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MCFGPIO_PCLRR_BUSCTL		0xFC0A4024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MCFGPIO_PCLRR_BE		0xFC0A4025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MCFGPIO_PCLRR_CS		0xFC0A4026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MCFGPIO_PCLRR_FECI2C		0xFC0A4027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MCFGPIO_PCLRR_QSPI		0xFC0A4028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MCFGPIO_PCLRR_TIMER		0xFC0A4029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MCFGPIO_PCLRR_UART		0xFC0A402A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MCFGPIO_PCLRR_FECH		0xFC0A402B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MCFGPIO_PCLRR_FECL		0xFC0A402C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * Generic GPIO support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCFGPIO_PODR			MCFGPIO_PODR_CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MCFGPIO_PDDR			MCFGPIO_PDDR_CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MCFGPIO_PPDR			MCFGPIO_PPDSDR_CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MCFGPIO_SETR			MCFGPIO_PPDSDR_CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MCFGPIO_CLRR			MCFGPIO_PCLRR_CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MCFGPIO_PIN_MAX			80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MCFGPIO_IRQ_MAX			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MCFGPIO_IRQ_VECBASE		MCFINT_VECBASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MCF_GPIO_PAR_UART		0xFC0A4036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MCF_GPIO_PAR_FECI2C		0xFC0A4033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MCF_GPIO_PAR_QSPI		0xFC0A4034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MCF_GPIO_PAR_FEC		0xFC0A4038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MCF_GPIO_PAR_UART_PAR_URXD0         (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MCF_GPIO_PAR_UART_PAR_UTXD0         (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MCF_GPIO_PAR_UART_PAR_URXD1         (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MCF_GPIO_PAR_UART_PAR_UTXD1         (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2   (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2   (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  *  PIT timer module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define	MCFPIT_BASE1		0xFC080000	/* Base address of TIMER1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define	MCFPIT_BASE2		0xFC084000	/* Base address of TIMER2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  *  UART module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MCFUART_BASE0		0xFC060000	/* Base address of UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MCFUART_BASE1		0xFC064000	/* Base address of UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MCFUART_BASE2		0xFC068000	/* Base address of UART2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  *  FEC module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define	MCFFEC_BASE0		0xFC030000	/* Base of FEC ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define	MCFFEC_SIZE0		0x800		/* Register set size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  *  QSPI module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define	MCFQSPI_BASE		0xFC05C000	/* Base of QSPI module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define	MCFQSPI_SIZE		0x40		/* Register set size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define	MCFQSPI_CS0		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define	MCFQSPI_CS1		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define	MCFQSPI_CS2		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  *  Reset Control Unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define	MCF_RCR			0xFC0A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define	MCF_RSR			0xFC0A0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  *  Power Management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MCFPM_WCR		0xfc040013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MCFPM_PPMSR0		0xfc04002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MCFPM_PPMCR0		0xfc04002d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MCFPM_PPMHR0		0xfc040030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MCFPM_PPMLR0		0xfc040034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MCFPM_LPCR		0xfc0a0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * I2C module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MCFI2C_BASE0		0xFC058000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MCFI2C_SIZE0		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #endif  /* m520xsim_h */