^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * m5206sim.h -- ColdFire 5206 System Integration Module support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef m5206sim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define m5206sim_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CPU_NAME "COLDFIRE(m5206)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CPU_INSTR_PER_JIFFY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MCF_BUSCLK MCF_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/m52xxacr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Define the 5206 SIM register set addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifdef CONFIG_M5206e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #ifdef CONFIG_M5206e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #if defined(CONFIG_NETtel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Define system peripheral IRQ usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCF_IRQ_I2C0 29 /* I2C, Level 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MCF_IRQ_UART0 73 /* UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MCF_IRQ_UART1 74 /* UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Generic GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MCFGPIO_PIN_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MCFGPIO_IRQ_VECBASE -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MCFGPIO_IRQ_MAX -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Some symbol defines for the Parallel Port Pin Assignment Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef CONFIG_M5206e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Clear to select T0 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Clear to select T0 output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Some symbol defines for the Interrupt Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MCFSIM_I2CICR MCFSIM_ICR11 /* I2C ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #ifdef CONFIG_M5206e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * I2C Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MCFI2C_BASE0 (MCF_MBAR + 0x1e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MCFI2C_SIZE0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif /* m5206sim_h */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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