Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _SUN3_INTERSIL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _SUN3_INTERSIL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /* bits 0 and 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define INTERSIL_FREQ_32K        0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define INTERSIL_FREQ_1M         0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define INTERSIL_FREQ_2M         0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define INTERSIL_FREQ_4M         0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define INTERSIL_12H_MODE   0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define INTERSIL_24H_MODE   0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define INTERSIL_STOP            0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define INTERSIL_RUN             0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define INTERSIL_INT_ENABLE     0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define INTERSIL_INT_DISABLE    0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define INTERSIL_MODE_NORMAL     0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define INTERSIL_MODE_TEST       0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define INTERSIL_HZ_100_MASK	 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct intersil_dt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	unsigned char	csec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	unsigned char	hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	unsigned char	minute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	unsigned char	second;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	unsigned char	month;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	unsigned char	day;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	unsigned char	year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	unsigned char	weekday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct intersil_7170 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	struct intersil_dt counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	struct intersil_dt alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	unsigned char	int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	unsigned char	cmd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) extern volatile char* clock_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define intersil_clock ((volatile struct intersil_7170 *) clock_va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define intersil_clear() (void)intersil_clock->int_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif