Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * include/asm-m68k/dma.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Hacked to fit Sun3x needs by Thomas Bogendoerfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef __M68K_DVMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define __M68K_DVMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define DVMA_PAGE_SHIFT	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DVMA_PAGE_SIZE	(1UL << DVMA_PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DVMA_PAGE_MASK	(~(DVMA_PAGE_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DVMA_PAGE_ALIGN(addr)	ALIGN(addr, DVMA_PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) extern void dvma_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 			  int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define dvma_malloc(x) dvma_malloc_align(x, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define dvma_map(x, y) dvma_map_align(x, y, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) extern unsigned long dvma_map_align(unsigned long kaddr, int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 			    int align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) extern void *dvma_malloc_align(unsigned long len, unsigned long align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) extern void dvma_unmap(void *baddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) extern void dvma_free(void *vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #ifdef CONFIG_SUN3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* sun3 dvma page support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* memory and pmegs potentially reserved for dvma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DVMA_PMEG_START 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DVMA_PMEG_END 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DVMA_START 0xf00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DVMA_END 0xfe0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DVMA_SIZE (DVMA_END-DVMA_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IOMMU_TOTAL_ENTRIES 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IOMMU_ENTRIES 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* empirical kludge -- dvma regions only seem to work right on 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)    byte boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DVMA_REGION_SIZE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)                          ~(DVMA_REGION_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* virt <-> phys conversions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define dvma_vtob(x) dvma_vtop(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define dvma_btov(x) dvma_ptov(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			       int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #else /* Sun3x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* sun3x dvma page support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define DVMA_START 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define DVMA_END 0xf00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DVMA_SIZE (DVMA_END-DVMA_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IOMMU_TOTAL_ENTRIES	   2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* the prom takes the top meg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define IOMMU_ENTRIES              (IOMMU_TOTAL_ENTRIES - 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define dvma_btov(x) ((unsigned long)(x) | 0xff000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) extern int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* everything below this line is specific to dma used for the onboard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)    ESP scsi on sun3x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /* Structure to describe the current status of DMA registers on the Sparc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) struct sparc_dma_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)   __volatile__ unsigned long cond_reg;	/* DMA condition register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)   __volatile__ unsigned long st_addr;	/* Start address of this transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)   __volatile__ unsigned long  cnt;	/* How many bytes to transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)   __volatile__ unsigned long dma_test;	/* DMA test register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* DVMA chip revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) enum dvma_rev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	dvmarev0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	dvmaesc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	dvmarev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	dvmarev2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	dvmarev3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	dvmarevplus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	dvmahme
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DMA_HASCOUNT(rev)  ((rev)==dvmaesc1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Linux DMA information structure, filled during probe. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct Linux_SBus_DMA {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct Linux_SBus_DMA *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct linux_sbus_device *SBus_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct sparc_dma_registers *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* Status, misc info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int node;                /* Prom node for this DMA device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	int running;             /* Are we doing DMA now? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	int allocated;           /* Are we "owned" by anyone yet? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* Transfer information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	unsigned long addr;      /* Start address of current transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	int nbytes;              /* Size of current transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int realbytes;           /* For splitting up large transfers, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* DMA revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	enum dvma_rev revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) extern struct Linux_SBus_DMA *dma_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Broken hardware... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DMA_ISBROKEN(dma)    ((dma)->revision == dvmarev1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DMA_ISESC1(dma)      ((dma)->revision == dvmaesc1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Fields in the cond_reg register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* First, the version identification bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DMA_DEVICE_ID    0xf0000000        /* Device identification bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DMA_VERS0        0x00000000        /* Sunray DMA version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DMA_ESCV1        0x40000000        /* DMA ESC Version 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DMA_VERS1        0x80000000        /* DMA rev 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DMA_VERS2        0xa0000000        /* DMA rev 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DMA_VERHME       0xb0000000        /* DMA hme gate array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DMA_VERSPLUS     0x90000000        /* DMA rev 1 PLUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DMA_HNDL_INTR    0x00000001        /* An IRQ needs to be handled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DMA_HNDL_ERROR   0x00000002        /* We need to take an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DMA_FIFO_ISDRAIN 0x0000000c        /* The DMA FIFO is draining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DMA_INT_ENAB     0x00000010        /* Turn on interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DMA_FIFO_INV     0x00000020        /* Invalidate the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DMA_ACC_SZ_ERR   0x00000040        /* The access size was bad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DMA_FIFO_STDRAIN 0x00000040        /* DMA_VERS1 Drain the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DMA_RST_SCSI     0x00000080        /* Reset the SCSI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DMA_RST_ENET     DMA_RST_SCSI      /* Reset the ENET controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DMA_ST_WRITE     0x00000100        /* write from device to memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DMA_ENABLE       0x00000200        /* Fire up DMA, handle requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DMA_PEND_READ    0x00000400        /* DMA_VERS1/0/PLUS Pending Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DMA_ESC_BURST    0x00000800        /* 1=16byte 0=32byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DMA_READ_AHEAD   0x00001800        /* DMA read ahead partial longword */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DMA_DSBL_RD_DRN  0x00001000        /* No EC drain on slave reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DMA_BCNT_ENAB    0x00002000        /* If on, use the byte counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DMA_TERM_CNTR    0x00004000        /* Terminal counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DMA_CSR_DISAB    0x00010000        /* No FIFO drains during csr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DMA_SCSI_DISAB   0x00020000        /* No FIFO drains during reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DMA_DSBL_WR_INV  0x00020000        /* No EC inval. on slave writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DMA_ADD_ENABLE   0x00040000        /* Special ESC DVMA optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DMA_E_BURST8	 0x00040000	   /* ENET: SBUS r/w burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DMA_BRST_SZ      0x000c0000        /* SCSI: SBUS r/w burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DMA_BRST64       0x00080000        /* SCSI: 64byte bursts (HME on UltraSparc only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DMA_BRST32       0x00040000        /* SCSI: 32byte bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DMA_BRST16       0x00000000        /* SCSI: 16byte bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DMA_BRST0        0x00080000        /* SCSI: no bursts (non-HME gate arrays) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DMA_ADDR_DISAB   0x00100000        /* No FIFO drains during addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DMA_2CLKS        0x00200000        /* Each transfer = 2 clock ticks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DMA_3CLKS        0x00400000        /* Each transfer = 3 clock ticks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DMA_EN_ENETAUI   DMA_3CLKS         /* Put lance into AUI-cable mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DMA_CNTR_DISAB   0x00800000        /* No IRQ when DMA_TERM_CNTR set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DMA_AUTO_NADDR   0x01000000        /* Use "auto nxt addr" feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DMA_SCSI_ON      0x02000000        /* Enable SCSI dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DMA_PARITY_OFF   0x02000000        /* HME: disable parity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DMA_LOADED_ADDR  0x04000000        /* Address has been loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DMA_LOADED_NADDR 0x08000000        /* Next address has been loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Values describing the burst-size property from the PROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DMA_BURST1       0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DMA_BURST2       0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DMA_BURST4       0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DMA_BURST8       0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DMA_BURST16      0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DMA_BURST32      0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DMA_BURST64      0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DMA_BURSTBITS    0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Determine highest possible final transfer address given a base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Yes, I hack a lot of elisp in my spare time... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DMA_ERROR_P(regs)  ((((regs)->cond_reg) & DMA_HNDL_ERROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DMA_IRQ_P(regs)    ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DMA_WRITE_P(regs)  ((((regs)->cond_reg) & DMA_ST_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DMA_OFF(regs)      ((((regs)->cond_reg) &= (~DMA_ENABLE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DMA_INTSOFF(regs)  ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DMA_INTSON(regs)   ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DMA_SETSTART(regs, addr)  ((((regs)->st_addr) = (char *) addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DMA_BEGINDMA_W(regs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)         ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DMA_BEGINDMA_R(regs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)         ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* For certain DMA chips, we need to disable ints upon irq entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  * and turn them back on when we are done.  So in any ESP interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * when leaving the handler.  You have been warned...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DMA_IRQ_ENTRY(dma, dregs) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)         if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)    } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DMA_IRQ_EXIT(dma, dregs) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)    } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Reset the friggin' thing... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DMA_RESET(dma) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct sparc_dma_registers *regs = dma->regs;                      \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* Let the current FIFO drain itself */                            \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN));                         \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* Reset the logic */                                              \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	regs->cond_reg |= (DMA_RST_SCSI);     /* assert */                 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	__delay(400);                         /* let the bits set ;) */    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	regs->cond_reg &= ~(DMA_RST_SCSI);    /* de-assert */              \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	sparc_dma_enable_interrupts(regs);    /* Re-enable interrupts */   \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/* Enable FAST transfers if available */                           \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS;            \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	dma->running = 0;                                                  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #endif /* !CONFIG_SUN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #endif /* !(__M68K_DVMA_H) */