^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _M68K_DMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _M68K_DMA_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifdef CONFIG_COLDFIRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * ColdFire DMA Model:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * ColdFire DMA supports two forms of DMA: Single and Dual address. Single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * address mode emits a source address, and expects that the device will either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * pick up the data (DMA READ) or source data (DMA WRITE). This implies that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the device will place data on the correct byte(s) of the data bus, as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * memory transactions are always 32 bits. This implies that only 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * devices will find single mode transfers useful. Dual address DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * performs two cycles: source read and destination write. ColdFire will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * align the data so that the device will always get the correct bytes, thus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * is useful for 8 and 16 bit devices. This is the mode that is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * AUG/25/2000 : added support for 8, 16 and 32-bit Single-Address-Mode (K)2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * APR/18/2002 : added proper support for MCF5272 DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Arthur Shipkowski (art@videon-central.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/mcfdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Set number of channels of DMA on ColdFire for different implementations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) defined(CONFIG_M528x) || defined(CONFIG_M525x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MAX_M68K_DMA_CHANNELS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #elif defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MAX_M68K_DMA_CHANNELS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #elif defined(CONFIG_M53xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MAX_M68K_DMA_CHANNELS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MAX_M68K_DMA_CHANNELS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #if !defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* I/O to memory, 8 bits, mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DMA_MODE_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* memory to I/O, 8 bits, mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DMA_MODE_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* I/O to memory, 16 bits, mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DMA_MODE_READ_WORD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* memory to I/O, 16 bits, mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DMA_MODE_WRITE_WORD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* I/O to memory, 32 bits, mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DMA_MODE_READ_LONG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* memory to I/O, 32 bits, mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DMA_MODE_WRITE_LONG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* I/O to memory, 8 bits, single-address-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DMA_MODE_READ_SINGLE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* memory to I/O, 8 bits, single-address-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DMA_MODE_WRITE_SINGLE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* I/O to memory, 16 bits, single-address-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DMA_MODE_READ_WORD_SINGLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* memory to I/O, 16 bits, single-address-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DMA_MODE_WRITE_WORD_SINGLE 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* I/O to memory, 32 bits, single-address-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DMA_MODE_READ_LONG_SINGLE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* memory to I/O, 32 bits, single-address-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DMA_MODE_WRITE_LONG_SINGLE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #else /* CONFIG_M5272 is defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Source static-address mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DMA_MODE_SRC_SA_BIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Two bits to select between all four modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DMA_MODE_SSIZE_MASK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Offset to shift bits in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DMA_MODE_SSIZE_OFF 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Destination static-address mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DMA_MODE_DES_SA_BIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Two bits to select between all four modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DMA_MODE_DSIZE_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Offset to shift bits in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DMA_MODE_DSIZE_OFF 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Size modifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DMA_MODE_SIZE_LONG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DMA_MODE_SIZE_BYTE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DMA_MODE_SIZE_WORD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DMA_MODE_SIZE_LINE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Aliases to help speed quick ports; these may be suboptimal, however. They
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * do not include the SINGLE mode modifiers since the MCF5272 does not have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * mode where the device is in control of its addressing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* I/O to memory, 8 bits, mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* memory to I/O, 8 bits, mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* I/O to memory, 16 bits, mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* memory to I/O, 16 bits, mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* I/O to memory, 32 bits, mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* memory to I/O, 32 bits, mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif /* !defined(CONFIG_M5272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #if !defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* enable/disable a specific DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static __inline__ void enable_dma(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) volatile unsigned short *dmawp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) printk("enable_dma(dmanr=%d)\n", dmanr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dmawp = (unsigned short *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static __inline__ void disable_dma(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) volatile unsigned short *dmawp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) volatile unsigned char *dmapb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) printk("disable_dma(dmanr=%d)\n", dmanr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dmawp = (unsigned short *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dmapb = (unsigned char *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Turn off external requests, and stop any DMA in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Clear the 'DMA Pointer Flip Flop'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Write 0 for LSB/MSB, 1 for MSB/LSB access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Use this once to initialize the FF to a known state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * After that, keep track of it. :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * --- In order to do that, the DMA routines below should ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * --- only be used while interrupts are disabled! ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * This is a NOP for ColdFire. Provide a stub for compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static __inline__ void clear_dma_ff(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* set mode (above) for a specific DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) volatile unsigned char *dmabp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) volatile unsigned short *dmawp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dmabp = (unsigned char *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dmawp = (unsigned short *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Clear config errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Set command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dmawp[MCFDMA_DCR] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MCFDMA_DCR_INT | /* Enable completion irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MCFDMA_DCR_CS | /* Force one xfer per request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MCFDMA_DCR_AA | /* Enable auto alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* single-address-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* sets s_rw (-> r/w) high if Memory to I/0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Memory to I/O or I/O to Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* 32 bit, 16 bit or 8 bit transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MCFDMA_DCR_SSIZE_BYTE)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MCFDMA_DCR_DSIZE_BYTE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #ifdef DEBUG_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Set transfer address for specific DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) volatile unsigned short *dmawp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) volatile unsigned int *dmalp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dmawp = (unsigned short *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dmalp = (unsigned int *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Determine which address registers are used for memory/device accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Source incrementing, must be memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dmalp[MCFDMA_SAR] = a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Set dest address, must be device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Destination incrementing, must be memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dmalp[MCFDMA_DAR] = a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Set source address, must be device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #ifdef DEBUG_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) (int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) (int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * Specific for Coldfire - sets device address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Should be called after the mode set call, and before set DMA address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dma_device_address[dmanr] = a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * NOTE 2: "count" represents _bytes_.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) volatile unsigned short *dmawp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dmawp = (unsigned short *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dmawp[MCFDMA_BCR] = (unsigned short)count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Get DMA residue count. After a DMA transfer, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * should return zero. Reading this while a DMA transfer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * still in progress will return unpredictable results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Otherwise, it returns the number of _bytes_ left to transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static __inline__ int get_dma_residue(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) volatile unsigned short *dmawp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned short count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) printk("get_dma_residue(dmanr=%d)\n", dmanr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dmawp = (unsigned short *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) count = dmawp[MCFDMA_BCR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return((int) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #else /* CONFIG_M5272 is defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * The MCF5272 DMA controller is very different than the controller defined above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * in terms of register mapping. For instance, with the exception of the 16-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * The big difference, however, is the lack of device-requested DMA. All modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * are dual address transfer, and there is no 'device' setup or direction bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * You can DMA between a device and memory, between memory and memory, or even between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * two devices directly, with any combination of incrementing and non-incrementing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * addresses you choose. This puts a crimp in distinguishing between the 'device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * address' set up by set_dma_device_addr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * which will act exactly as above in -- it will look to see if the source is set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * autoincrement, and if so it will make the source use the set_dma_addr value and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * destination the set_dma_device_addr value. Otherwise the source will be set to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * set_dma_device_addr value and the destination will get the set_dma_addr value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * and make it explicit. Depending on what you're doing, one of these two should work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * for you, but don't mix them in the same transfer setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* enable/disable a specific DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static __inline__ void enable_dma(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) volatile unsigned int *dmalp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) printk("enable_dma(dmanr=%d)\n", dmanr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dmalp = (unsigned int *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static __inline__ void disable_dma(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) volatile unsigned int *dmalp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) printk("disable_dma(dmanr=%d)\n", dmanr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dmalp = (unsigned int *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Turn off external requests, and stop any DMA in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Clear the 'DMA Pointer Flip Flop'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * Write 0 for LSB/MSB, 1 for MSB/LSB access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Use this once to initialize the FF to a known state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * After that, keep track of it. :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * --- In order to do that, the DMA routines below should ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * --- only be used while interrupts are disabled! ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * This is a NOP for ColdFire. Provide a stub for compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static __inline__ void clear_dma_ff(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* set mode (above) for a specific DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) volatile unsigned int *dmalp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) volatile unsigned short *dmawp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dmalp = (unsigned int *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dmawp = (unsigned short *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Clear config errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Set command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dmalp[MCFDMA_DMR] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MCFDMA_DMR_RQM_DUAL | /* Mandatory Request Mode setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MCFDMA_DMR_DSTT_SD | /* Set up addressing types; set to supervisor-data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MCFDMA_DMR_SRCT_SD | /* Set up addressing types; set to supervisor-data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* source static-address-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* dest static-address-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #ifdef DEBUG_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dmanr, (int) &dmalp[MCFDMA_DMR], dmalp[MCFDMA_DMR],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) (int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Set transfer address for specific DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) volatile unsigned int *dmalp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dmalp = (unsigned int *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Determine which address registers are used for memory/device accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Source incrementing, must be memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dmalp[MCFDMA_DSAR] = a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Set dest address, must be device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Destination incrementing, must be memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dmalp[MCFDMA_DDAR] = a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Set source address, must be device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #ifdef DEBUG_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) __FILE__, __LINE__, dmanr, (int) &dmalp[MCFDMA_DMR], dmalp[MCFDMA_DMR],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) (int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) (int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Specific for Coldfire - sets device address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Should be called after the mode set call, and before set DMA address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dma_device_address[dmanr] = a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * NOTE 2: "count" represents _bytes_.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) volatile unsigned int *dmalp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dmalp = (unsigned int *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dmalp[MCFDMA_DBCR] = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * Get DMA residue count. After a DMA transfer, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * should return zero. Reading this while a DMA transfer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * still in progress will return unpredictable results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Otherwise, it returns the number of _bytes_ left to transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static __inline__ int get_dma_residue(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) volatile unsigned int *dmalp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #ifdef DMA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) printk("get_dma_residue(dmanr=%d)\n", dmanr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dmalp = (unsigned int *) dma_base_addr[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) count = dmalp[MCFDMA_DBCR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return(count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #endif /* !defined(CONFIG_M5272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #endif /* CONFIG_COLDFIRE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* it's useless on the m68k, but unfortunately needed by the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) bootmem allocator (but this should do it for this) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define MAX_DMA_ADDRESS PAGE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define MAX_DMA_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) extern void free_dma(unsigned int dmanr); /* release it again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) extern int isa_dma_bridge_buggy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define isa_dma_bridge_buggy (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #endif /* _M68K_DMA_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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