Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	coldfire.h -- Motorola ColdFire CPU sepecific defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	(C) Copyright 1999-2006, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *	(C) Copyright 2000, Lineo (www.lineo.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef	coldfire_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define	coldfire_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  *	Define master clock frequency. This is done at config time now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  *	No point enumerating dozens of possible clock options here. And
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  *	in any case new boards come along from time to time that have yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  *	another different clocking frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifdef CONFIG_CLOCK_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define	MCF_CLK		CONFIG_CLOCK_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #error "Don't know what your ColdFire CPU clock frequency is??"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  *	Define the processor internal peripherals base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  *	The majority of ColdFire parts use an MBAR register to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  *	the base address. Some have an IPSBAR register instead, and it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  *	has slightly different rules on its size and alignment. Some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  *	parts have fixed addresses and the internal peripherals cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  *	be relocated in the CPU address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  *	The value of MBAR or IPSBAR is config time selectable, we no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  *	longer hard define it here. No MBAR or IPSBAR will be defined if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  *	this part has a fixed peripheral address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifdef CONFIG_MBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define	MCF_MBAR	CONFIG_MBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifdef CONFIG_IPSBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define	MCF_IPSBAR	CONFIG_IPSBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif	/* coldfire_h */