^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _M68K_BVME6000HW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _M68K_BVME6000HW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * PIT structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define BVME_PIT_BASE 0xffa00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) unsigned char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) pad_a[3], pgcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) pad_b[3], psrr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) pad_c[3], paddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) pad_d[3], pbddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) pad_e[3], pcddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) pad_f[3], pivr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) pad_g[3], pacr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) pad_h[3], pbcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) pad_i[3], padr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) pad_j[3], pbdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) pad_k[3], paar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) pad_l[3], pbar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) pad_m[3], pcdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pad_n[3], psr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) pad_o[3], res1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) pad_p[3], res2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) pad_q[3], tcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) pad_r[3], tivr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) pad_s[3], res3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) pad_t[3], cprh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) pad_u[3], cprm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) pad_v[3], cprl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) pad_w[3], res4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) pad_x[3], crh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) pad_y[3], crm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) pad_z[3], crl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) pad_A[3], tsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) pad_B[3], res5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) } PitRegs_t, *PitRegsPtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define bvmepit ((*(volatile PitRegsPtr)(BVME_PIT_BASE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BVME_RTC_BASE 0xff900000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) pad_a[3], msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pad_b[3], t0cr_rtmr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pad_c[3], t1cr_omr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pad_d[3], pfr_icr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) pad_e[3], irr_icr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pad_f[3], bcd_tenms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pad_g[3], bcd_sec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pad_h[3], bcd_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pad_i[3], bcd_hr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pad_j[3], bcd_dom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pad_k[3], bcd_mth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pad_l[3], bcd_year,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pad_m[3], bcd_ujcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pad_n[3], bcd_hjcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pad_o[3], bcd_dow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pad_p[3], t0lsb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pad_q[3], t0msb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pad_r[3], t1lsb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pad_s[3], t1msb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pad_t[3], cmp_sec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pad_u[3], cmp_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pad_v[3], cmp_hr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pad_w[3], cmp_dom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pad_x[3], cmp_mth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pad_y[3], cmp_dow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pad_z[3], sav_sec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pad_A[3], sav_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pad_B[3], sav_hr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pad_C[3], sav_dom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pad_D[3], sav_mth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pad_E[3], ram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pad_F[3], test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) } RtcRegs_t, *RtcPtr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BVME_I596_BASE 0xff100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BVME_ETHIRQ_REG 0xff20000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BVME_LOCAL_IRQ_STAT 0xff20000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BVME_ETHERR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BVME_ABORT_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BVME_NCR53C710_BASE 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BVME_SCC_A_ADDR 0xffb0000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BVME_SCC_B_ADDR 0xffb00003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BVME_SCC_RTxC 7372800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BVME_CONFIG_REG 0xff500003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define config_reg_ptr (volatile unsigned char *)BVME_CONFIG_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BVME_CONFIG_SW1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BVME_CONFIG_SW2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BVME_CONFIG_SW3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BVME_CONFIG_SW4 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BVME_IRQ_TYPE_PRIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BVME_IRQ_PRN (IRQ_USER+20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BVME_IRQ_TIMER (IRQ_USER+25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BVME_IRQ_I596 IRQ_AUTO_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BVME_IRQ_SCSI IRQ_AUTO_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BVME_IRQ_RTC IRQ_AUTO_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BVME_IRQ_ABORT IRQ_AUTO_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* SCC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BVME_IRQ_SCC_BASE IRQ_USER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BVME_IRQ_SCCB_TX IRQ_USER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BVME_IRQ_SCCB_STAT (IRQ_USER+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BVME_IRQ_SCCB_RX (IRQ_USER+4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BVME_IRQ_SCCB_SPCOND (IRQ_USER+6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BVME_IRQ_SCCA_TX (IRQ_USER+8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BVME_IRQ_SCCA_STAT (IRQ_USER+10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BVME_IRQ_SCCA_RX (IRQ_USER+12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BVME_IRQ_SCCA_SPCOND (IRQ_USER+14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Address control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BVME_ACR_A32VBA 0xff400003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BVME_ACR_A32MSK 0xff410003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BVME_ACR_A24VBA 0xff420003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define BVME_ACR_A24MSK 0xff430003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BVME_ACR_A16VBA 0xff440003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define BVME_ACR_A32LBA 0xff450003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BVME_ACR_A24LBA 0xff460003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define BVME_ACR_ADDRCTL 0xff470003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define bvme_acr_a32vba *(volatile unsigned char *)BVME_ACR_A32VBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define bvme_acr_a32msk *(volatile unsigned char *)BVME_ACR_A32MSK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define bvme_acr_a24vba *(volatile unsigned char *)BVME_ACR_A24VBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define bvme_acr_a24msk *(volatile unsigned char *)BVME_ACR_A24MSK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define bvme_acr_a16vba *(volatile unsigned char *)BVME_ACR_A16VBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define bvme_acr_a32lba *(volatile unsigned char *)BVME_ACR_A32LBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define bvme_acr_a24lba *(volatile unsigned char *)BVME_ACR_A24LBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define bvme_acr_addrctl *(volatile unsigned char *)BVME_ACR_ADDRCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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