^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ** linux/atarihw.h -- This header defines some macros and pointers for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ** the various Atari custom hardware registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ** Copyright 1994 by Björn Brauel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) ** 5/1/94 Roman Hodek:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ** Added definitions for TT specific chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) ** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ** Finally added definitions for the matrix/codec and the DSP56001 host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ** interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ** This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ** License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ** for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifndef _LINUX_ATARIHW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define _LINUX_ATARIHW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/bootinfo-atari.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/kmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) extern u_long atari_mch_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) extern u_long atari_mch_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) extern u_long atari_switches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) extern int atari_rtc_year_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) extern int atari_dont_touch_floppy_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) extern int atari_SCC_reset_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) extern ssize_t atari_nvram_read(char *, size_t, loff_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) extern ssize_t atari_nvram_write(char *, size_t, loff_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) extern ssize_t atari_nvram_get_size(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern long atari_nvram_set_checksum(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) extern long atari_nvram_initialize(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* convenience macros for testing machine type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) (atari_mch_cookie & 0xffff) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) (atari_mch_cookie & 0xffff) == 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* values for atari_switches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ATARI_SWITCH_IKBD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ATARI_SWITCH_MIDI 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ATARI_SWITCH_SND6 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ATARI_SWITCH_SND7 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ATARI_SWITCH_OVSC_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ATARI_SWITCH_OVSC_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Define several Hardware-Chips for indication so that for the ATARI we do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * no longer decide whether it is a Falcon or other machine . It's just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * important what hardware the machine uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ATARIHW_DECLARE(name) unsigned name : 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ATARIHW_SET(name) (atari_hw_present.name = 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ATARIHW_PRESENT(name) (atari_hw_present.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct atari_hw_present {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* video hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* sound hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* disk storage interfaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ATARIHW_DECLARE(IDE); /* IDE Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* other I/O hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) without it... but who knows?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) and Falcon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* real time clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* supporting hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ATARIHW_DECLARE(SCU); /* System Control Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ATARIHW_DECLARE(BLITTER); /* Blitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ATARIHW_DECLARE(VME); /* VME Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) extern struct atari_hw_present atari_hw_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Reading the MFP port register gives a machine independent delay, since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * MFP always has a 8 MHz clock. This avoids problems with the varying length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * of nops on various machines. Somebody claimed that the tstb takes 600 ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MFPDELAY() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __asm__ __volatile__ ( "tstb %0" : : "m" (st_mfp.par_dt_reg) : "cc" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Do cache push/invalidate for DMA read/write. This function obeys the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * snooping on some machines (Medusa) and processors: The Medusa itself can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * snoop, but only the '040 can source data from its cache to DMA writes i.e.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * reads from memory). Both '040 and '060 invalidate cache entries on snooped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * DMA reads (i.e., writes to memory).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline void dma_cache_maintenance( unsigned long paddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int writeflag )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (writeflag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!MACH_IS_MEDUSA || CPU_IS_060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) cache_push( paddr, len );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!MACH_IS_MEDUSA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) cache_clear( paddr, len );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ** Shifter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ST_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ST_MID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ST_HIGH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TT_LOW 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TT_MID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TT_HIGH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SHF_BAS (0xffff8200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct SHIFTER_ST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u_char pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u_char bas_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u_char pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u_char bas_md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u_char pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u_char volatile vcounthi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u_char pad4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u_char volatile vcountmid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u_char pad5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u_char volatile vcountlow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u_char volatile syncmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u_char pad6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u_char pad7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u_char bas_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) # define shifter_st ((*(volatile struct SHIFTER_ST *)SHF_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SHF_FBAS (0xffff820e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct SHIFTER_F030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u_short off_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u_short scn_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) # define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SHF_TBAS (0xffff8200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct SHIFTER_TT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u_char char_dummy0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u_char bas_hi; /* video mem base addr, high and mid byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u_char char_dummy1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u_char bas_md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u_char char_dummy2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u_char vcount_hi; /* pointer to currently displayed byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u_char char_dummy3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u_char vcount_md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u_char char_dummy4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u_char vcount_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u_short st_sync; /* ST compatible sync mode register, unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u_char char_dummy5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u_char bas_lo; /* video mem addr, low byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u_char char_dummy6[2+3*16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* $ffff8240: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u_short color_reg[16]; /* 16 color registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u_char st_shiftmode; /* ST compatible shift mode register, unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u_char char_dummy7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u_short tt_shiftmode; /* TT shift mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* values for shifter_tt->tt_shiftmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TT_SHIFTER_STLOW 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TT_SHIFTER_STMID 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TT_SHIFTER_STHIGH 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TT_SHIFTER_TTLOW 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TT_SHIFTER_TTMID 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TT_SHIFTER_TTHIGH 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TT_SHIFTER_MODEMASK 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TT_SHIFTER_NUMMODE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TT_SHIFTER_PALETTE_MASK 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TT_SHIFTER_GRAYMODE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* 256 TT palette registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TT_PALETTE_BASE (0xffff8400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define tt_palette ((volatile u_short *)TT_PALETTE_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TT_PALETTE_RED_MASK 0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TT_PALETTE_GREEN_MASK 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TT_PALETTE_BLUE_MASK 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ** Falcon030 VIDEL Video Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ** for description see File 'linux\tools\atari\hardware.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define f030_col ((u_long *) 0xffff9800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define f030_xreg ((u_short*) 0xffff8282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define f030_yreg ((u_short*) 0xffff82a2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define f030_creg ((u_short*) 0xffff82c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define f030_sreg ((u_short*) 0xffff8260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define f030_mreg ((u_short*) 0xffff820a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define f030_linewidth ((u_short*) 0xffff820e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define f030_hscroll ((u_char*) 0xffff8265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define VIDEL_BAS (0xffff8260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct VIDEL {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u_short st_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u_short pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u_char xoffset_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u_char xoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u_short f_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u_char pad2[0x1a];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u_short hht;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u_short hbb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u_short hbe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u_short hdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u_short hde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u_short hss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u_char pad3[0x14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u_short vft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u_short vbb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u_short vbe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u_short vdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u_short vde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u_short vss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u_char pad4[0x12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u_short control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u_short mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define videl ((*(volatile struct VIDEL *)VIDEL_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ** DMA/WD1772 Disk Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define FWD_BAS (0xffff8604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct DMA_WD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u_short fdc_acces_seccount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u_short dma_mode_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u_char dma_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u_char char_dummy2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u_char dma_md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u_char char_dummy3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u_char dma_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u_short fdc_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) # define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* alias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define st_dma dma_wd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* The two highest bytes of an extended DMA as a short; this is a must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * for the Medusa.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ** YM2149 Sound Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ** access in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define YM_BAS (0xffff8800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct SOUND_YM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u_char rd_data_reg_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u_char char_dummy1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u_char wd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* TT SCSI DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define TT_SCSI_DMA_BAS (0xffff8700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct TT_DMA {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u_char char_dummy0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u_char dma_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u_char char_dummy1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u_char dma_addr_hmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u_char char_dummy2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u_char dma_addr_lmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u_char char_dummy3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u_char dma_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u_char char_dummy4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u_char dma_cnt_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u_char char_dummy5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u_char dma_cnt_hmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u_char char_dummy6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u_char dma_cnt_lmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u_char char_dummy7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u_char dma_cnt_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u_long dma_restdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u_short dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* TT SCSI Controller 5380 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define TT_5380_BAS (0xffff8781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct TT_5380 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u_char scsi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u_char char_dummy1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u_char scsi_icr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u_char char_dummy2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u_char scsi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u_char char_dummy3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u_char scsi_tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u_char char_dummy4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u_char scsi_idstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u_char char_dummy5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u_char scsi_dmastat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u_char char_dummy6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u_char scsi_targrcv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u_char char_dummy7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u_char scsi_inircv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define tt_scsi_regp ((volatile char *)TT_5380_BAS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ** Falcon DMA Sound Subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define MATRIX_BASE (0xffff8930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct MATRIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u_short source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u_short destination;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u_char external_frequency_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u_char internal_frequency_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CODEC_BASE (0xffff8936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u_char tracks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u_char input_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CODEC_SOURCE_ADC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CODEC_SOURCE_MATRIX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u_char adc_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define ADC_SOURCE_RIGHT_PSG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define ADC_SOURCE_LEFT_PSG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u_char gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define CODEC_GAIN_RIGHT 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define CODEC_GAIN_LEFT 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u_char attenuation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define CODEC_ATTENUATION_RIGHT 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define CODEC_ATTENUATION_LEFT 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u_char unused1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u_char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define CODEC_OVERFLOW_RIGHT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define CODEC_OVERFLOW_LEFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u_char unused2, unused3, unused4, unused5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u_char gpio_directions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define CODEC_GPIO_IN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CODEC_GPIO_OUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u_char unused6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u_char gpio_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define falcon_codec (*(volatile struct CODEC *)CODEC_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ** Falcon Blitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define BLT_BAS (0xffff8a00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct BLITTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u_short halftone[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u_short src_x_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u_short src_y_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u_long src_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u_short endmask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u_short endmask2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u_short endmask3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u_short dst_x_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u_short dst_y_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u_long dst_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u_short wd_per_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u_short ln_per_bb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u_short hlf_op_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u_short log_op_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u_short lin_nm_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u_short skew_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) # define blitter ((*(volatile struct BLITTER *)BLT_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ** SCC Z8530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SCC_BAS (0xffff8c81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct SCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u_char cha_a_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u_char char_dummy1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u_char cha_a_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u_char char_dummy2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u_char cha_b_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u_char char_dummy3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u_char cha_b_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) # define atari_scc ((*(volatile struct SCC*)SCC_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* The ESCC (Z85230) in an Atari ST. The channels are reversed! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) # define st_escc ((*(volatile struct SCC*)0xfffffa31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) # define st_escc_dsr ((*(volatile char *)0xfffffa39))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* TT SCC DMA Controller (same chip as SCSI DMA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define TT_SCC_DMA_BAS (0xffff8c00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ** VIDEL Palette Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define FPL_BAS (0xffff9800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct VIDEL_PALETTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u_long reg[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) # define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ** Falcon DSP Host Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define DSP56K_HOST_INTERFACE_BASE (0xffffa200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct DSP56K_HOST_INTERFACE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u_char icr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define DSP56K_ICR_RREQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define DSP56K_ICR_TREQ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define DSP56K_ICR_HF0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define DSP56K_ICR_HF1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define DSP56K_ICR_HM0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define DSP56K_ICR_HM1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define DSP56K_ICR_INIT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u_char cvr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define DSP56K_CVR_HV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define DSP56K_CVR_HC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u_char isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define DSP56K_ISR_RXDF 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define DSP56K_ISR_TXDE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define DSP56K_ISR_TRDY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define DSP56K_ISR_HF2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define DSP56K_ISR_HF3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define DSP56K_ISR_DMA 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define DSP56K_ISR_HREQ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u_char ivr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u_char b[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u_short w[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u_long l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) } data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ** MFP 68901
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define MFP_BAS (0xfffffa01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct MFP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u_char par_dt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u_char char_dummy1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u_char active_edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u_char char_dummy2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u_char data_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u_char char_dummy3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u_char int_en_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u_char char_dummy4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u_char int_en_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u_char char_dummy5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u_char int_pn_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u_char char_dummy6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u_char int_pn_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u_char char_dummy7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u_char int_sv_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u_char char_dummy8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u_char int_sv_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u_char char_dummy9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u_char int_mk_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u_char char_dummy10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u_char int_mk_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u_char char_dummy11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u_char vec_adr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u_char char_dummy12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u_char tim_ct_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u_char char_dummy13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u_char tim_ct_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u_char char_dummy14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u_char tim_ct_cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u_char char_dummy15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u_char tim_dt_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u_char char_dummy16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u_char tim_dt_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u_char char_dummy17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u_char tim_dt_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u_char char_dummy18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u_char tim_dt_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u_char char_dummy19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u_char sync_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u_char char_dummy20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u_char usart_ctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u_char char_dummy21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u_char rcv_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u_char char_dummy22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u_char trn_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u_char char_dummy23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u_char usart_dta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) # define st_mfp ((*(volatile struct MFP*)MFP_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* TT's second MFP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define TT_MFP_BAS (0xfffffa81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) # define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* TT System Control Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define TT_SCU_BAS (0xffff8e01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct TT_SCU {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u_char sys_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u_char char_dummy1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u_char sys_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u_char char_dummy2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u_char softint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u_char char_dummy3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u_char vmeint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u_char char_dummy4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u_char gp_reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u_char char_dummy5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u_char gp_reg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u_char char_dummy6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u_char vme_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u_char char_dummy7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u_char vme_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* TT real time clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define TT_RTC_BAS (0xffff8961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct TT_RTC {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u_char regsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u_char dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u_char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ** ACIA 6850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* constants for the ACIA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* baudrate selection and reset (Baudrate = clock/factor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define ACIA_DIV1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define ACIA_DIV16 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define ACIA_DIV64 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define ACIA_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* character format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* transmit control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* receive control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define ACIA_RID (0<<7) /* RxINT disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define ACIA_RIE (1<<7) /* RxINT enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* status fields of the ACIA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define ACIA_RDRF 1 /* Receive Data Register Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define ACIA_DCD (1<<2) /* Data Carrier Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define ACIA_CTS (1<<3) /* Clear To Send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define ACIA_FE (1<<4) /* Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define ACIA_OVRN (1<<5) /* Receiver Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define ACIA_PE (1<<6) /* Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define ACIA_IRQ (1<<7) /* Interrupt Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define ACIA_BAS (0xfffffc00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct ACIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u_char key_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u_char char_dummy1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u_char key_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u_char char_dummy2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u_char mid_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u_char char_dummy3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u_char mid_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) # define acia ((*(volatile struct ACIA*)ACIA_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define TT_DMASND_BAS (0xffff8900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct TT_DMASND {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u_char int_ctrl; /* Falcon: Interrupt control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u_char ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u_char pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u_char bas_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u_char pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u_char bas_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u_char pad4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u_char bas_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u_char pad5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u_char addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u_char pad6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u_char addr_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u_char pad7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u_char addr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u_char pad8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u_char end_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u_char pad9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u_char end_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u_char pad10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u_char end_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u_char pad11[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u_char track_select; /* Falcon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u_char mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u_char pad12[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Falcon only: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u_short cbar_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u_short cbar_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u_char ext_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u_char int_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u_char rec_track_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u_char dac_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u_char adc_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u_char input_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u_short output_atten;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) # define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define DMASND_MFP_INT_REPLAY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define DMASND_MFP_INT_RECORD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define DMASND_TIMERA_INT_REPLAY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define DMASND_TIMERA_INT_RECORD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define DMASND_CTRL_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define DMASND_CTRL_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define DMASND_CTRL_REPEAT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define DMASND_CTRL_RECORD_ON 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define DMASND_CTRL_RECORD_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define DMASND_CTRL_RECORD_REPEAT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define DMASND_CTRL_SELECT_REPLAY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define DMASND_CTRL_SELECT_RECORD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define DMASND_MODE_MONO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define DMASND_MODE_STEREO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define DMASND_MODE_8BIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define DMASND_MODE_16BIT 0x40 /* Falcon only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define DMASND_MODE_12KHZ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define DMASND_MODE_25KHZ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define DMASND_MODE_50KHZ 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define DMASNDSetBase(bufstart) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) } while( 0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) (tt_dmasnd.addr_mid << 8) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) (tt_dmasnd.addr_low))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define DMASNDSetEnd(bufend) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) } while( 0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define TT_MICROWIRE_BAS (0xffff8922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct TT_MICROWIRE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u_short data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) u_short mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) # define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define MW_LM1992_ADDR 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define MW_LM1992_VOLUME(dB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) (0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define MW_LM1992_BALLEFT(dB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) (0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define MW_LM1992_BALRIGHT(dB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) (0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define MW_LM1992_TREBLE(dB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) (0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define MW_LM1992_BASS(dB) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) (0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define MW_LM1992_PSG_LOW 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define MW_LM1992_PSG_HIGH 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define MW_LM1992_PSG_OFF 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define MSTE_RTC_BAS (0xfffffc21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct MSTE_RTC {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u_char sec_ones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u_char dummy1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u_char sec_tens;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u_char dummy2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u_char min_ones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u_char dummy3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u_char min_tens;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u_char dummy4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u_char hr_ones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u_char dummy5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u_char hr_tens;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u_char dummy6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u_char weekday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u_char dummy7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) u_char day_ones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u_char dummy8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u_char day_tens;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u_char dummy9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u_char mon_ones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u_char dummy10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u_char mon_tens;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) u_char dummy11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u_char year_ones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u_char dummy12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u_char year_tens;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u_char dummy13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u_char mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u_char dummy14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u_char test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u_char dummy15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u_char reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ** EtherNAT add-on card for Falcon - combined ethernet and USB adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define ATARI_ETHERNAT_PHYS_ADDR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #endif /* linux/atarihw.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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