Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) ** asm-m68k/pcmcia.h -- Amiga Linux PCMCIA Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) ** Copyright 1997 by Alain Malek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) ** This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) ** License.  See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) ** for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) ** Created: 12/10/97 by Alain Malek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #ifndef __AMIGA_PCMCIA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define __AMIGA_PCMCIA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/amigayle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* prototypes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) void pcmcia_reset(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) int pcmcia_copy_tuple(unsigned char tuple_id, void *tuple, int max_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) void pcmcia_program_voltage(int voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) void pcmcia_access_speed(int speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) void pcmcia_write_enable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) void pcmcia_write_disable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static inline u_char pcmcia_read_status(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	return (gayle.cardstatus & 0x7c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static inline u_char pcmcia_get_intreq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	return (gayle.intreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static inline void pcmcia_ack_int(u_char intreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	gayle.intreq = 0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static inline void pcmcia_enable_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	gayle.inten |= GAYLE_IRQ_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static inline void pcmcia_disable_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	gayle.inten &= ~GAYLE_IRQ_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PCMCIA_INSERTED	(gayle.cardstatus & GAYLE_CS_CCDET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* valid voltages for pcmcia_ProgramVoltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PCMCIA_0V	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PCMCIA_5V	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PCMCIA_12V	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* valid speeds for pcmcia_AccessSpeed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PCMCIA_SPEED_100NS	100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define PCMCIA_SPEED_150NS	150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define PCMCIA_SPEED_250NS	250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define PCMCIA_SPEED_720NS	720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* PCMCIA Tuple codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CISTPL_NULL		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CISTPL_DEVICE		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CISTPL_LONGLINK_CB	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CISTPL_CONFIG_CB	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CISTPL_CFTABLE_ENTRY_CB	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CISTPL_LONGLINK_MFC	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CISTPL_BAR		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CISTPL_CHECKSUM		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CISTPL_LONGLINK_A	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CISTPL_LONGLINK_C	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CISTPL_LINKTARGET	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CISTPL_NO_LINK		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CISTPL_VERS_1		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CISTPL_ALTSTR		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CISTPL_DEVICE_A		0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CISTPL_JEDEC_C		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CISTPL_JEDEC_A		0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CISTPL_CONFIG		0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CISTPL_CFTABLE_ENTRY	0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CISTPL_DEVICE_OC	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CISTPL_DEVICE_OA	0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CISTPL_DEVICE_GEO	0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CISTPL_DEVICE_GEO_A	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CISTPL_MANFID		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CISTPL_FUNCID		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CISTPL_FUNCE		0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CISTPL_SWIL		0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CISTPL_END		0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /* FUNCID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CISTPL_FUNCID_MULTI	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CISTPL_FUNCID_MEMORY	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CISTPL_FUNCID_SERIAL	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CISTPL_FUNCID_PARALLEL	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CISTPL_FUNCID_FIXED	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CISTPL_FUNCID_VIDEO	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CISTPL_FUNCID_NETWORK	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CISTPL_FUNCID_AIMS	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CISTPL_FUNCID_SCSI	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif