^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Bare & Hare Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on include/asm-m68knommu/MC68332.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The Silver Hammer Group, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * M68VZ328 fixes by Evan Stawnyczy <evan@lineo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * vz multiport fixes by Michael Leslie <mleslie@lineo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef _MC68VZ328_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define _MC68VZ328_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BYTE_REF(addr) (*((volatile unsigned char*)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define WORD_REF(addr) (*((volatile unsigned short*)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LONG_REF(addr) (*((volatile unsigned long*)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 0xFFFFF0xx -- System Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * System Control Register (SCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SCR_ADDR 0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SCR BYTE_REF(SCR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCR_DMAP 0x04 /* Double Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCR_SO 0x08 /* Supervisor Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SCR_PRV 0x20 /* Privilege Violation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SCR_WPV 0x40 /* Write Protect Violation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCR_BETO 0x80 /* Bus-Error TimeOut */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MRR_ADDR 0xfffff004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MRR LONG_REF(MRR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 0xFFFFF1xx -- Chip-Select logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Chip Select Group Base Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CSGBA_ADDR 0xfffff100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CSGBB_ADDR 0xfffff102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CSGBC_ADDR 0xfffff104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CSGBD_ADDR 0xfffff106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CSGBA WORD_REF(CSGBA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CSGBB WORD_REF(CSGBB_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CSGBC WORD_REF(CSGBC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CSGBD WORD_REF(CSGBD_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Chip Select Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CSA_ADDR 0xfffff110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CSB_ADDR 0xfffff112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CSC_ADDR 0xfffff114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CSD_ADDR 0xfffff116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CSA WORD_REF(CSA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CSB WORD_REF(CSB_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CSC WORD_REF(CSC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CSD WORD_REF(CSD_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CSA_EN 0x0001 /* Chip-Select Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CSA_SIZ_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CSA_WS_MASK 0x0070 /* Wait State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CSA_WS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CSA_BSW 0x0080 /* Data Bus Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CSA_FLASH 0x0100 /* FLASH Memory Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CSA_RO 0x8000 /* Read-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CSB_EN 0x0001 /* Chip-Select Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CSB_SIZ_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CSB_WS_MASK 0x0070 /* Wait State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CSB_WS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CSB_BSW 0x0080 /* Data Bus Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CSB_FLASH 0x0100 /* FLASH Memory Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CSB_UPSIZ_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CSB_ROP 0x2000 /* Readonly if protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CSB_SOP 0x4000 /* Supervisor only if protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CSB_RO 0x8000 /* Read-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CSC_EN 0x0001 /* Chip-Select Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CSC_SIZ_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CSC_WS_MASK 0x0070 /* Wait State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CSC_WS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CSC_BSW 0x0080 /* Data Bus Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CSC_FLASH 0x0100 /* FLASH Memory Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CSC_UPSIZ_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CSC_ROP 0x2000 /* Readonly if protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CSC_SOP 0x4000 /* Supervisor only if protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CSC_RO 0x8000 /* Read-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CSD_EN 0x0001 /* Chip-Select Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CSD_SIZ_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CSD_WS_MASK 0x0070 /* Wait State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CSD_WS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CSD_BSW 0x0080 /* Data Bus Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CSD_FLASH 0x0100 /* FLASH Memory Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CSD_DRAM 0x0200 /* Dram Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CSD_COMB 0x0400 /* Combining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CSD_UPSIZ_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CSD_ROP 0x2000 /* Readonly if protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CSD_SOP 0x4000 /* Supervisor only if protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CSD_RO 0x8000 /* Read-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * Emulation Chip-Select Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define EMUCS_ADDR 0xfffff118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define EMUCS WORD_REF(EMUCS_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define EMUCS_WS_MASK 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EMUCS_WS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * PLL Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PLLCR_ADDR 0xfffff200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PLLCR WORD_REF(PLLCR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PLLCR_DISPLL 0x0008 /* Disable PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PLLCR_PRESC 0x0020 /* VCO prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PLLCR_SYSCLK_SEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PLLCR_LCDCLK_SEL_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * PLL Frequency Select Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PLLFSR_ADDR 0xfffff202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PLLFSR WORD_REF(PLLFSR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PLLFSR_PC_MASK 0x00ff /* P Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PLLFSR_PC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PLLFSR_QC_MASK 0x0f00 /* Q Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PLLFSR_QC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PLLFSR_PROT 0x4000 /* Protect P & Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Power Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PCTRL_ADDR 0xfffff207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PCTRL BYTE_REF(PCTRL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PCTRL_WIDTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PCTRL_PCEN 0x80 /* Power Control Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * 0xFFFFF3xx -- Interrupt Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Interrupt Vector Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IVR_ADDR 0xfffff300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IVR BYTE_REF(IVR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IVR_VECTOR_MASK 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Interrupt control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ICR_ADDR 0xfffff302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ICR WORD_REF(ICR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Interrupt Mask Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IMR_ADDR 0xfffff304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IMR LONG_REF(IMR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * Define the names for bit positions first. This is useful for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * request_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SPI2_IRQ_NUM 0 /* SPI 2 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TMR_IRQ_NUM 1 /* Timer 1 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define UART1_IRQ_NUM 2 /* UART 1 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define RTC_IRQ_NUM 4 /* RTC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TMR2_IRQ_NUM 5 /* Timer 2 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define KB_IRQ_NUM 6 /* Keyboard Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define INT0_IRQ_NUM 8 /* External INT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define INT1_IRQ_NUM 9 /* External INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define INT2_IRQ_NUM 10 /* External INT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define INT3_IRQ_NUM 11 /* External INT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define UART2_IRQ_NUM 12 /* UART 2 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IRQ1_IRQ_NUM 16 /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IRQ2_IRQ_NUM 17 /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IRQ3_IRQ_NUM 18 /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IRQ6_IRQ_NUM 19 /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IRQ5_IRQ_NUM 20 /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SPI1_IRQ_NUM 21 /* SPI 1 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SPI_IRQ_NUM SPI2_IRQ_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SPIM_IRQ_NUM SPI_IRQ_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TMR1_IRQ_NUM TMR_IRQ_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define UART_IRQ_NUM UART1_IRQ_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * Here go the bitmasks themselves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IMR_MSPIM IMR_MSPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IMR_MTMR1 IMR_MTMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ISR_ADDR 0xfffff30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ISR LONG_REF(ISR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define ISR_SPIM ISR_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define ISR_TMR1 ISR_TMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Interrupt Pending Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IPR_ADDR 0xfffff30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IPR LONG_REF(IPR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IPR_SPIM IPR_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IPR_TMR1 IPR_TMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * 0xFFFFF4xx -- Parallel Ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Port A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define PADIR_ADDR 0xfffff400 /* Port A direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define PADATA_ADDR 0xfffff401 /* Port A data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define PADIR BYTE_REF(PADIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PADATA BYTE_REF(PADATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PAPUEN BYTE_REF(PAPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PA(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * Port B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define PBDATA_ADDR 0xfffff409 /* Port B data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define PBDIR BYTE_REF(PBDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PBDATA BYTE_REF(PBDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define PBPUEN BYTE_REF(PBPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define PBSEL BYTE_REF(PBSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PB(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define PB_PWMO 0x80 /* Use PWMO as PB[7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Port C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define PCDATA_ADDR 0xfffff411 /* Port C data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define PCDIR BYTE_REF(PCDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define PCDATA BYTE_REF(PCDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PCPDEN BYTE_REF(PCPDEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define PCSEL BYTE_REF(PCSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define PC(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PC_LD0 0x01 /* Use LD0 as PC[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define PC_LD1 0x02 /* Use LD1 as PC[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PC_LD2 0x04 /* Use LD2 as PC[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define PC_LD3 0x08 /* Use LD3 as PC[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define PC_LFLM 0x10 /* Use LFLM as PC[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define PC_LLP 0x20 /* Use LLP as PC[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define PC_LCLK 0x40 /* Use LCLK as PC[6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PC_LACD 0x80 /* Use LACD as PC[7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Port D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PDDATA_ADDR 0xfffff419 /* Port D data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PDSEL_ADDR 0xfffff41b /* Port D Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define PDDIR BYTE_REF(PDDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define PDDATA BYTE_REF(PDDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PDPUEN BYTE_REF(PDPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define PDSEL BYTE_REF(PDSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PDPOL BYTE_REF(PDPOL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PDKBEN BYTE_REF(PDKBEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define PDIQEG BYTE_REF(PDIQEG_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define PD(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define PD_INT0 0x01 /* Use INT0 as PD[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define PD_INT1 0x02 /* Use INT1 as PD[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define PD_INT2 0x04 /* Use INT2 as PD[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define PD_INT3 0x08 /* Use INT3 as PD[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Port E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define PEDATA_ADDR 0xfffff421 /* Port E data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define PESEL_ADDR 0xfffff423 /* Port E Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define PEDIR BYTE_REF(PEDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define PEDATA BYTE_REF(PEDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define PEPUEN BYTE_REF(PEPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define PESEL BYTE_REF(PESEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define PE(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define PE_DWE 0x08 /* Use DWE as PE[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define PE_RXD 0x10 /* Use RXD as PE[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define PE_TXD 0x20 /* Use TXD as PE[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define PE_RTS 0x40 /* Use RTS as PE[6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define PE_CTS 0x80 /* Use CTS as PE[7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * Port F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define PFDATA_ADDR 0xfffff429 /* Port F data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define PFDIR BYTE_REF(PFDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define PFDATA BYTE_REF(PFDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define PFPUEN BYTE_REF(PFPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define PFSEL BYTE_REF(PFSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define PF(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define PF_CLKO 0x04 /* Use CLKO as PF[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define PF_A20 0x08 /* Use A20 as PF[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define PF_A21 0x10 /* Use A21 as PF[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define PF_A22 0x20 /* Use A22 as PF[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define PF_A23 0x40 /* Use A23 as PF[6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * Port G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define PGDATA_ADDR 0xfffff431 /* Port G data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define PGDIR BYTE_REF(PGDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define PGDATA BYTE_REF(PGDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define PGPUEN BYTE_REF(PGPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define PGSEL BYTE_REF(PGSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define PG(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define PG_A0 0x02 /* Use A0 as PG[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * Port J
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define PJDATA_ADDR 0xfffff439 /* Port J data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enb. reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define PJSEL_ADDR 0xfffff43B /* Port J Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define PJDIR BYTE_REF(PJDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define PJDATA BYTE_REF(PJDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define PJPUEN BYTE_REF(PJPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define PJSEL BYTE_REF(PJSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define PJ(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * Port K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define PKDATA_ADDR 0xfffff441 /* Port K data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enb. reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define PKSEL_ADDR 0xfffff443 /* Port K Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define PKDIR BYTE_REF(PKDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define PKDATA BYTE_REF(PKDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define PKPUEN BYTE_REF(PKPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define PKSEL BYTE_REF(PKSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define PK(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define PK_DATAREADY 0x01 /* Use ~DATA_READY as PK[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define PK_PWM2 0x01 /* Use PWM2 as PK[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define PK_R_W 0x02 /* Use R/W as PK[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define PK_LDS 0x04 /* Use /LDS as PK[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define PK_UDS 0x08 /* Use /UDS as PK[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define PK_LD4 0x10 /* Use LD4 as PK[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define PK_LD5 0x20 /* Use LD5 as PK[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define PK_LD6 0x40 /* Use LD6 as PK[6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define PK_LD7 0x80 /* Use LD7 as PK[7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define PJDATA_ADDR 0xfffff439 /* Port J data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define PJSEL_ADDR 0xfffff43B /* Port J Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define PJDIR BYTE_REF(PJDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define PJDATA BYTE_REF(PJDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define PJPUEN BYTE_REF(PJPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define PJSEL BYTE_REF(PJSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define PJ(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define PJ_MOSI 0x01 /* Use MOSI as PJ[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define PJ_MISO 0x02 /* Use MISO as PJ[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define PJ_SPICLK1 0x04 /* Use SPICLK1 as PJ[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define PJ_SS 0x08 /* Use SS as PJ[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define PJ_RXD2 0x10 /* Use RXD2 as PJ[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define PJ_TXD2 0x20 /* Use TXD2 as PJ[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define PJ_RTS2 0x40 /* Use RTS2 as PJ[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define PJ_CTS2 0x80 /* Use CTS2 as PJ[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * Port M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define PMDIR_ADDR 0xfffff448 /* Port M direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define PMDATA_ADDR 0xfffff449 /* Port M data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define PMSEL_ADDR 0xfffff44b /* Port M Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define PMDIR BYTE_REF(PMDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define PMDATA BYTE_REF(PMDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define PMPUEN BYTE_REF(PMPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define PMSEL BYTE_REF(PMSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define PM(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define PM_SDCE 0x02 /* Use SDCE as PM[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define PM_DQMH 0x04 /* Use DQMH as PM[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define PM_DQML 0x08 /* Use DQML as PM[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define PM_SDA10 0x10 /* Use SDA10 as PM[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define PM_DMOE 0x20 /* Use DMOE as PM[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * PWM Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define PWMC_ADDR 0xfffff500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define PWMC WORD_REF(PWMC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define PWMC_CLKSEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define PWMC_REPEAT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define PWMC_EN 0x0010 /* Enable PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define PMNC_FIFOAV 0x0020 /* FIFO Available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define PWMC_PRESCALER_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define PWMC_CLKSRC 0x8000 /* Clock Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define PWMC_PWMEN PWMC_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * PWM Sample Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define PWMS_ADDR 0xfffff502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define PWMS WORD_REF(PWMS_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * PWM Period Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define PWMP_ADDR 0xfffff504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define PWMP BYTE_REF(PWMP_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * PWM Counter Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define PWMCNT_ADDR 0xfffff505
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define PWMCNT BYTE_REF(PWMCNT_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * 0xFFFFF6xx -- General-Purpose Timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * Timer Control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define TCTL_ADDR 0xfffff600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define TCTL WORD_REF(TCTL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define TCTL_TEN 0x0001 /* Timer Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define TCTL_IRQEN 0x0010 /* IRQ Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define TCTL_OM 0x0020 /* Output Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define TCTL_FRR 0x0010 /* Free-Run Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define TCTL1_ADDR TCTL_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define TCTL1 TCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * Timer Prescaler Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define TPRER_ADDR 0xfffff602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define TPRER WORD_REF(TPRER_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define TPRER1_ADDR TPRER_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define TPRER1 TPRER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * Timer Compare Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define TCMP_ADDR 0xfffff604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define TCMP WORD_REF(TCMP_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define TCMP1_ADDR TCMP_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define TCMP1 TCMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * Timer Capture register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define TCR_ADDR 0xfffff606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define TCR WORD_REF(TCR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define TCR1_ADDR TCR_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define TCR1 TCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * Timer Counter Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define TCN_ADDR 0xfffff608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define TCN WORD_REF(TCN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define TCN1_ADDR TCN_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define TCN1 TCN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * Timer Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define TSTAT_ADDR 0xfffff60a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define TSTAT WORD_REF(TSTAT_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define TSTAT_COMP 0x0001 /* Compare Event occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define TSTAT_CAPT 0x0001 /* Capture Event occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define TSTAT1_ADDR TSTAT_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define TSTAT1 TSTAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * SPIM Data Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define SPIMDATA_ADDR 0xfffff800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define SPIMDATA WORD_REF(SPIMDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * SPIM Control/Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define SPIMCONT_ADDR 0xfffff802
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define SPIMCONT WORD_REF(SPIMCONT_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define SPIMCONT_BIT_COUNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define SPIMCONT_IRQ 0x0080 /* Interrupt Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define SPIMCONT_XCH 0x0100 /* Exchange */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define SPIMCONT_DATA_RATE_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define SPIMCONT_SPIMIRQ SPIMCONT_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define SPIMCONT_SPIMEN SPIMCONT_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * 0xFFFFF9xx -- UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * UART Status/Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define USTCNT_ADDR 0xfffff900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define USTCNT WORD_REF(USTCNT_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define USTCNT_STOP 0x0200 /* Stop bit transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define USTCNT_ODD 0x0400 /* Odd Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define USTCNT_PEN 0x0800 /* Parity Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define USTCNT_CLKM 0x1000 /* Clock Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define USTCNT_TXEN 0x2000 /* Transmitter Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define USTCNT_RXEN 0x4000 /* Receiver Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define USTCNT_UEN 0x8000 /* UART Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define USTCNT_TXAVAILEN USTCNT_TXAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define USTCNT_TXHALFEN USTCNT_TXHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define USTCNT_TXEMPTYEN USTCNT_TXEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define USTCNT_RXREADYEN USTCNT_RXRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define USTCNT_RXHALFEN USTCNT_RXHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define USTCNT_RXFULLEN USTCNT_RXFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define USTCNT_CTSDELTAEN USTCNT_CTSD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define USTCNT_ODD_EVEN USTCNT_ODD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define USTCNT_PARITYEN USTCNT_PEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define USTCNT_CLKMODE USTCNT_CLKM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define USTCNT_UARTEN USTCNT_UEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * UART Baud Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define UBAUD_ADDR 0xfffff902
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define UBAUD WORD_REF(UBAUD_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define UBAUD_PRESCALER_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define UBAUD_DIVIDE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * UART Receiver Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define URX_ADDR 0xfffff904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define URX WORD_REF(URX_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define URX_RXDATA_ADDR 0xfffff905
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define URX_RXDATA_MASK 0x00ff /* Received data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define URX_RXDATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define URX_PARITY_ERROR 0x0100 /* Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define URX_BREAK 0x0200 /* Break Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define URX_FRAME_ERROR 0x0400 /* Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define URX_OVRUN 0x0800 /* Serial Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define URX_OLD_DATA 0x1000 /* Old data in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define URX_FIFO_FULL 0x8000 /* FIFO is Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * UART Transmitter Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define UTX_ADDR 0xfffff906
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define UTX WORD_REF(UTX_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define UTX_TXDATA_ADDR 0xfffff907
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define UTX_TXDATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define UTX_CTS_DELTA 0x0100 /* CTS changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define UTX_CTS_STAT 0x0200 /* CTS State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define UTX_NOCTS 0x0800 /* Ignore CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define UTX_CTS_STATUS UTX_CTS_STAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define UTX_IGNORE_CTS UTX_NOCTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * UART Miscellaneous Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define UMISC_ADDR 0xfffff908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define UMISC WORD_REF(UMISC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define UMISC_TX_POL 0x0004 /* Transmit Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define UMISC_RX_POL 0x0008 /* Receive Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define UMISC_RTS 0x0040 /* Set RTS status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define UMISC_RTSCONT 0x0080 /* Choose RTS control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define UMISC_CLKSRC 0x4000 /* Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * UART Non-integer Prescaler Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define NIPR_ADDR 0xfffff90a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define NIPR WORD_REF(NIPR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define NIPR_STEP_VALUE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define NIPR_SELECT_MASK 0x0700 /* Tap Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define NIPR_SELECT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* generalization of uart control registers to support multiple ports: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) volatile unsigned short int ustcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) volatile unsigned short int ubaud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) volatile unsigned short int w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) volatile unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) volatile unsigned char rxdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) } urx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) volatile unsigned short int w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) volatile unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) volatile unsigned char txdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) } utx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) volatile unsigned short int umisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) volatile unsigned short int nipr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) volatile unsigned short int hmark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) volatile unsigned short int unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) } __packed m68328_uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * 0xFFFFFAxx -- LCD Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * LCD Screen Starting Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define LSSA_ADDR 0xfffffa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define LSSA LONG_REF(LSSA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * LCD Virtual Page Width Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define LVPW_ADDR 0xfffffa05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define LVPW BYTE_REF(LVPW_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * LCD Screen Width Register (not compatible with '328 !!!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define LXMAX_ADDR 0xfffffa08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define LXMAX WORD_REF(LXMAX_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * LCD Screen Height Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define LYMAX_ADDR 0xfffffa0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define LYMAX WORD_REF(LYMAX_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * LCD Cursor X Position Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define LCXP_ADDR 0xfffffa18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define LCXP WORD_REF(LCXP_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define LCXP_CC_MASK 0xc000 /* Cursor Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define LCXP_CC_TRAMSPARENT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define LCXP_CC_BLACK 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define LCXP_CC_REVERSED 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define LCXP_CC_WHITE 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define LCXP_CXP_MASK 0x02ff /* Cursor X position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * LCD Cursor Y Position Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define LCYP_ADDR 0xfffffa1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define LCYP WORD_REF(LCYP_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * LCD Cursor Width and Heigth Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define LCWCH_ADDR 0xfffffa1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define LCWCH WORD_REF(LCWCH_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define LCWCH_CH_MASK 0x001f /* Cursor Height */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define LCWCH_CH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define LCWCH_CW_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * LCD Blink Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define LBLKC_ADDR 0xfffffa1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define LBLKC BYTE_REF(LBLKC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define LBLKC_BD_MASK 0x7f /* Blink Divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define LBLKC_BD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define LBLKC_BKEN 0x80 /* Blink Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * LCD Panel Interface Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define LPICF_ADDR 0xfffffa20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define LPICF BYTE_REF(LPICF_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define LPICF_GS_BW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define LPICF_GS_GRAY_4 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define LPICF_GS_GRAY_16 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define LPICF_PBSIZ_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define LPICF_PBSIZ_2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define LPICF_PBSIZ_4 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * LCD Polarity Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define LPOLCF_ADDR 0xfffffa21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define LPOLCF BYTE_REF(LPOLCF_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * LACD (LCD Alternate Crystal Direction) Rate Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define LACDRC_ADDR 0xfffffa23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define LACDRC BYTE_REF(LACDRC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define LACDRC_ACDSLT 0x80 /* Signal Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define LACDRC_ACD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * LCD Pixel Clock Divider Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define LPXCD_ADDR 0xfffffa25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define LPXCD BYTE_REF(LPXCD_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define LPXCD_PCD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * LCD Clocking Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define LCKCON_ADDR 0xfffffa27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define LCKCON BYTE_REF(LCKCON_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define LCKCON_DWS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define LCKCON_DWIDTH 0x40 /* Display Memory Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define LCKCON_LCDON 0x80 /* Enable LCD Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define LCKCON_DW_MASK LCKCON_DWS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * LCD Refresh Rate Adjustment Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define LRRA_ADDR 0xfffffa29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define LRRA BYTE_REF(LRRA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * LCD Panning Offset Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define LPOSR_ADDR 0xfffffa2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define LPOSR BYTE_REF(LPOSR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define LPOSR_POS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * LCD Frame Rate Control Modulation Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define LFRCM_ADDR 0xfffffa31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define LFRCM BYTE_REF(LFRCM_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define LFRCM_YMOD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define LFRCM_XMOD_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * LCD Gray Palette Mapping Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define LGPMR_ADDR 0xfffffa33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define LGPMR BYTE_REF(LGPMR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define LGPMR_G1_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define LGPMR_G1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define LGPMR_G2_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define LGPMR_G2_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * PWM Contrast Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define PWMR_ADDR 0xfffffa36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define PWMR WORD_REF(PWMR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define PWMR_PW_MASK 0x00ff /* Pulse Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define PWMR_PW_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define PWMR_CCPEN 0x0100 /* Contrast Control Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define PWMR_SRC_LINE 0x0000 /* Line Pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define PWMR_SRC_LCD 0x4000 /* LCD clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * 0xFFFFFBxx -- Real-Time Clock (RTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * RTC Hours Minutes and Seconds Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define RTCTIME_ADDR 0xfffffb00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define RTCTIME LONG_REF(RTCTIME_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define RTCTIME_SECONDS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define RTCTIME_MINUTES_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define RTCTIME_HOURS_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * RTC Alarm Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define RTCALRM_ADDR 0xfffffb04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define RTCALRM LONG_REF(RTCALRM_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define RTCALRM_SECONDS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define RTCALRM_MINUTES_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define RTCALRM_HOURS_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * Watchdog Timer Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define WATCHDOG_ADDR 0xfffffb0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define WATCHDOG WORD_REF(WATCHDOG_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define WATCHDOG_EN 0x0001 /* Watchdog Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define WATCHDOG_CNT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * RTC Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define RTCCTL_ADDR 0xfffffb0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define RTCCTL WORD_REF(RTCCTL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define RTCCTL_XTL 0x0020 /* Crystal Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define RTCCTL_EN 0x0080 /* RTC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define RTCCTL_384 RTCCTL_XTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define RTCCTL_ENABLE RTCCTL_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * RTC Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define RTCISR_ADDR 0xfffffb0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define RTCISR WORD_REF(RTCISR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define RTCISR_SW 0x0001 /* Stopwatch timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * RTC Interrupt Enable Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define RTCIENR_ADDR 0xfffffb10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define RTCIENR WORD_REF(RTCIENR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * Stopwatch Minutes Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define STPWCH_ADDR 0xfffffb12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define STPWCH WORD_REF(STPWCH_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define SPTWCH_CNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * RTC Day Count Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define DAYR_ADDR 0xfffffb1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define DAYR WORD_REF(DAYR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define DAYR_DAYS_MASK 0x1ff /* Day Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define DAYR_DAYS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * RTC Day Alarm Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define DAYALARM_ADDR 0xfffffb1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define DAYALARM WORD_REF(DAYALARM_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define DAYALARM_DAYSAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * 0xFFFFFCxx -- DRAM Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * DRAM Memory Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define DRAMMC_ADDR 0xfffffc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define DRAMMC WORD_REF(DRAMMC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define DRAMMC_ROW12_PA10 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define DRAMMC_ROW12_PA21 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define DRAMMC_ROW12_PA23 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define DRAMMC_ROW0_PA11 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define DRAMMC_ROW0_PA22 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define DRAMMC_ROW0_PA23 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define DRAMMC_REF_MASK 0x001f /* Refresh Cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define DRAMMC_REF_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * DRAM Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define DRAMC_ADDR 0xfffffc02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define DRAMC WORD_REF(DRAMC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define DRAMC_DWE 0x0001 /* DRAM Write Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define DRAMC_SLW 0x0008 /* Slow RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define DRAMC_LSP 0x0010 /* Light Sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define DRAMC_MSW 0x0020 /* Slow Multiplexing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define DRAMC_WS_MASK 0x00c0 /* Wait-states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define DRAMC_WS_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define DRAMC_PGSZ_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define DRAMC_PGSZ_256K 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define DRAMC_PGSZ_512K 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define DRAMC_PGSZ_1024K 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define DRAMC_PGSZ_2048K 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define DRAMC_EDO 0x0400 /* EDO DRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define DRAMC_BC_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define DRAMC_RM 0x4000 /* Refresh Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define DRAMC_EN 0x8000 /* DRAM Controller enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * ICE Module Address Compare Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define ICEMACR_ADDR 0xfffffd00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define ICEMACR LONG_REF(ICEMACR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) * ICE Module Address Mask Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define ICEMAMR_ADDR 0xfffffd04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define ICEMAMR LONG_REF(ICEMAMR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * ICE Module Control Compare Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define ICEMCCR_ADDR 0xfffffd08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define ICEMCCR WORD_REF(ICEMCCR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * ICE Module Control Mask Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define ICEMCMR_ADDR 0xfffffd0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define ICEMCMR WORD_REF(ICEMCMR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * ICE Module Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define ICEMCR_ADDR 0xfffffd0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define ICEMCR WORD_REF(ICEMCR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define ICEMCR_CEN 0x0001 /* Compare Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define ICEMCR_PBEN 0x0002 /* Program Break Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define ICEMCR_SB 0x0004 /* Single Breakpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define ICEMCR_HMDIS 0x0008 /* HardMap disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * ICE Module Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define ICEMSR_ADDR 0xfffffd0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define ICEMSR WORD_REF(ICEMSR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define ICEMSR_EMUEN 0x0001 /* Emulation Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #endif /* _MC68VZ328_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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