^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* include/asm-m68knommu/MC68328.h: '328 control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Bear & Hare Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on include/asm-m68knommu/MC68332.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef _MC68328_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define _MC68328_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BYTE_REF(addr) (*((volatile unsigned char*)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define WORD_REF(addr) (*((volatile unsigned short*)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LONG_REF(addr) (*((volatile unsigned long*)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 0xFFFFF0xx -- System Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * System Control Register (SCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SCR_ADDR 0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SCR BYTE_REF(SCR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SCR_DMAP 0x04 /* Double Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SCR_SO 0x08 /* Supervisor Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCR_PRV 0x20 /* Privilege Violation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCR_WPV 0x40 /* Write Protect Violation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCR_BETO 0x80 /* Bus-Error TimeOut */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Mask Revision Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MRR_ADDR 0xfffff004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MRR LONG_REF(MRR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 0xFFFFF1xx -- Chip-Select logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Group Base Address Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GRPBASEA_ADDR 0xfffff100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GRPBASEB_ADDR 0xfffff102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GRPBASEC_ADDR 0xfffff104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GRPBASED_ADDR 0xfffff106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GRPBASEA WORD_REF(GRPBASEA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GRPBASEB WORD_REF(GRPBASEB_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GRPBASEC WORD_REF(GRPBASEC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GRPBASED WORD_REF(GRPBASED_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GRPBASE_V 0x0001 /* Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Group Base Address Mask Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GRPMASKA_ADDR 0xfffff108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GRPMASKB_ADDR 0xfffff10a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GRPMASKC_ADDR 0xfffff10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GRPMASKD_ADDR 0xfffff10e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GRPMASKA WORD_REF(GRPMASKA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GRPMASKB WORD_REF(GRPMASKB_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GRPMASKC WORD_REF(GRPMASKC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GRPMASKD WORD_REF(GRPMASKD_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GRMMASK_GMA_MASK 0xfffff0 /* Group Base Mask (bits 31-20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Chip-Select Option Registers (group A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CSA0_ADDR 0xfffff110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CSA1_ADDR 0xfffff114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CSA2_ADDR 0xfffff118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CSA3_ADDR 0xfffff11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CSA0 LONG_REF(CSA0_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CSA1 LONG_REF(CSA1_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CSA2 LONG_REF(CSA2_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CSA3 LONG_REF(CSA3_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CSA_WAIT_MASK 0x00000007 /* Wait State Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CSA_WAIT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CSA_RO 0x00000008 /* Read-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CSA_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CSA_AM_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CSA_BUSW 0x00010000 /* Bus Width Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CSA_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CSA_AC_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Chip-Select Option Registers (group B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CSB0_ADDR 0xfffff120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CSB1_ADDR 0xfffff124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CSB2_ADDR 0xfffff128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CSB3_ADDR 0xfffff12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CSB0 LONG_REF(CSB0_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CSB1 LONG_REF(CSB1_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CSB2 LONG_REF(CSB2_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CSB3 LONG_REF(CSB3_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CSB_WAIT_MASK 0x00000007 /* Wait State Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CSB_WAIT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CSB_RO 0x00000008 /* Read-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CSB_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CSB_AM_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CSB_BUSW 0x00010000 /* Bus Width Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CSB_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CSB_AC_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Chip-Select Option Registers (group C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CSC0_ADDR 0xfffff130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CSC1_ADDR 0xfffff134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CSC2_ADDR 0xfffff138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CSC3_ADDR 0xfffff13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CSC0 LONG_REF(CSC0_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CSC1 LONG_REF(CSC1_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CSC2 LONG_REF(CSC2_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CSC3 LONG_REF(CSC3_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CSC_WAIT_MASK 0x00000007 /* Wait State Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CSC_WAIT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CSC_RO 0x00000008 /* Read-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CSC_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CSC_AM_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CSC_BUSW 0x00010000 /* Bus Width Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CSC_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CSC_AC_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Chip-Select Option Registers (group D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CSD0_ADDR 0xfffff140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CSD1_ADDR 0xfffff144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CSD2_ADDR 0xfffff148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CSD3_ADDR 0xfffff14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CSD0 LONG_REF(CSD0_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CSD1 LONG_REF(CSD1_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CSD2 LONG_REF(CSD2_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CSD3 LONG_REF(CSD3_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CSD_WAIT_MASK 0x00000007 /* Wait State Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CSD_WAIT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CSD_RO 0x00000008 /* Read-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CSD_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CSD_AM_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CSD_BUSW 0x00010000 /* Bus Width Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CSD_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CSD_AC_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * PLL Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PLLCR_ADDR 0xfffff200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PLLCR WORD_REF(PLLCR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PLLCR_DISPLL 0x0008 /* Disable PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PLLCR_SYSCLK_SEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PLLCR_PIXCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PLLCR_PIXCLK_SEL_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PLLCR_LCDCLK_SEL_MASK PLLCR_PIXCLK_SEL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define PLLCR_LCDCLK_SEL_SHIFT PLLCR_PIXCLK_SEL_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * PLL Frequency Select Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PLLFSR_ADDR 0xfffff202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PLLFSR WORD_REF(PLLFSR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PLLFSR_PC_MASK 0x00ff /* P Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PLLFSR_PC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PLLFSR_QC_MASK 0x0f00 /* Q Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PLLFSR_QC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PLLFSR_PROT 0x4000 /* Protect P & Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Power Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PCTRL_ADDR 0xfffff207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PCTRL BYTE_REF(PCTRL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PCTRL_WIDTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PCTRL_STOP 0x40 /* Enter power-save mode immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PCTRL_PCEN 0x80 /* Power Control Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * 0xFFFFF3xx -- Interrupt Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Interrupt Vector Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IVR_ADDR 0xfffff300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IVR BYTE_REF(IVR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IVR_VECTOR_MASK 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Interrupt control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ICR_ADRR 0xfffff302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ICR WORD_REF(ICR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Interrupt Mask Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IMR_ADDR 0xfffff304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IMR LONG_REF(IMR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Define the names for bit positions first. This is useful for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * request_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SPIM_IRQ_NUM 0 /* SPI Master interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TMR2_IRQ_NUM 1 /* Timer 2 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define UART_IRQ_NUM 2 /* UART interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define RTC_IRQ_NUM 4 /* RTC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define KB_IRQ_NUM 6 /* Keyboard Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define INT0_IRQ_NUM 8 /* External INT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define INT1_IRQ_NUM 9 /* External INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define INT2_IRQ_NUM 10 /* External INT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define INT3_IRQ_NUM 11 /* External INT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define INT4_IRQ_NUM 12 /* External INT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define INT5_IRQ_NUM 13 /* External INT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define INT6_IRQ_NUM 14 /* External INT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define INT7_IRQ_NUM 15 /* External INT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IRQ1_IRQ_NUM 16 /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IRQ2_IRQ_NUM 17 /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IRQ3_IRQ_NUM 18 /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IRQ6_IRQ_NUM 19 /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PEN_IRQ_NUM 20 /* Pen Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SPIS_IRQ_NUM 21 /* SPI Slave Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TMR1_IRQ_NUM 22 /* Timer 1 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IRQ7_IRQ_NUM 23 /* IRQ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* '328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SPI_IRQ_NUM SPIM_IRQ_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TMR_IRQ_NUM TMR1_IRQ_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Here go the bitmasks themselves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define IMR_MSPIM (1 << SPIM_IRQ_NUM) /* Mask SPI Master interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IMR_MINT4 (1 << INT4_IRQ_NUM) /* Mask External INT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IMR_MINT5 (1 << INT5_IRQ_NUM) /* Mask External INT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IMR_MINT6 (1 << INT6_IRQ_NUM) /* Mask External INT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IMR_MINT7 (1 << INT7_IRQ_NUM) /* Mask External INT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define IMR_MPEN (1 << PEN_IRQ_NUM) /* Mask Pen Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define IMR_MSPIS (1 << SPIS_IRQ_NUM) /* Mask SPI Slave Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define IMR_MTMR1 (1 << TMR1_IRQ_NUM) /* Mask Timer 1 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IMR_MIRQ7 (1 << IRQ7_IRQ_NUM) /* Mask IRQ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IMR_MSPI IMR_MSPIM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define IMR_MTMR IMR_MTMR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Interrupt Wake-Up Enable Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define IWR_ADDR 0xfffff308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IWR LONG_REF(IWR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IWR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IWR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IWR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IWR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IWR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IWR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IWR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IWR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IWR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IWR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IWR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define IWR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IWR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IWR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define IWR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define IWR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define IWR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define IWR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define IWR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define IWR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define ISR_ADDR 0xfffff30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define ISR LONG_REF(ISR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define ISR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define ISR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define ISR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define ISR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define ISR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define ISR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define ISR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define ISR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define ISR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define ISR_SPI ISR_SPIM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define ISR_TMR ISR_TMR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * Interrupt Pending Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define IPR_ADDR 0xfffff310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define IPR LONG_REF(IPR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define IPR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define IPR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define IPR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define IPR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define IPR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define IPR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define IPR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define IPR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define IPR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define IPR_SPI IPR_SPIM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define IPR_TMR IPR_TMR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * 0xFFFFF4xx -- Parallel Ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Port A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define PADIR_ADDR 0xfffff400 /* Port A direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define PADATA_ADDR 0xfffff401 /* Port A data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PASEL_ADDR 0xfffff403 /* Port A Select register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define PADIR BYTE_REF(PADIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define PADATA BYTE_REF(PADATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define PASEL BYTE_REF(PASEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define PA(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define PA_A(x) PA((x) - 16) /* This is specific to PA only! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define PA_A16 PA(0) /* Use A16 as PA(0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define PA_A17 PA(1) /* Use A17 as PA(1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define PA_A18 PA(2) /* Use A18 as PA(2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define PA_A19 PA(3) /* Use A19 as PA(3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define PA_A20 PA(4) /* Use A20 as PA(4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define PA_A21 PA(5) /* Use A21 as PA(5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define PA_A22 PA(6) /* Use A22 as PA(6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define PA_A23 PA(7) /* Use A23 as PA(7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Port B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define PBDATA_ADDR 0xfffff409 /* Port B data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define PBDIR BYTE_REF(PBDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define PBDATA BYTE_REF(PBDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define PBSEL BYTE_REF(PBSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define PB(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define PB_D(x) PB(x) /* This is specific to port B only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define PB_D0 PB(0) /* Use D0 as PB(0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define PB_D1 PB(1) /* Use D1 as PB(1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define PB_D2 PB(2) /* Use D2 as PB(2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define PB_D3 PB(3) /* Use D3 as PB(3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define PB_D4 PB(4) /* Use D4 as PB(4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define PB_D5 PB(5) /* Use D5 as PB(5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define PB_D6 PB(6) /* Use D6 as PB(6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define PB_D7 PB(7) /* Use D7 as PB(7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * Port C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define PCDATA_ADDR 0xfffff411 /* Port C data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define PCDIR BYTE_REF(PCDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define PCDATA BYTE_REF(PCDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define PCSEL BYTE_REF(PCSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define PC(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define PC_WE PC(6) /* Use WE as PC(6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define PC_DTACK PC(5) /* Use DTACK as PC(5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define PC_IRQ7 PC(4) /* Use IRQ7 as PC(4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define PC_LDS PC(2) /* Use LDS as PC(2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define PC_UDS PC(1) /* Use UDS as PC(1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define PC_MOCLK PC(0) /* Use MOCLK as PC(0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * Port D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define PDDATA_ADDR 0xfffff419 /* Port D data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define PDDIR BYTE_REF(PDDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define PDDATA BYTE_REF(PDDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define PDPUEN BYTE_REF(PDPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define PDPOL BYTE_REF(PDPOL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define PDIQEG BYTE_REF(PDIQEG_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define PD(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define PD_KB(x) PD(x) /* This is specific for Port D only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define PD_KB0 PD(0) /* Use KB0 as PD(0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define PD_KB1 PD(1) /* Use KB1 as PD(1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define PD_KB2 PD(2) /* Use KB2 as PD(2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define PD_KB3 PD(3) /* Use KB3 as PD(3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define PD_KB4 PD(4) /* Use KB4 as PD(4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define PD_KB5 PD(5) /* Use KB5 as PD(5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define PD_KB6 PD(6) /* Use KB6 as PD(6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define PD_KB7 PD(7) /* Use KB7 as PD(7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Port E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define PEDATA_ADDR 0xfffff421 /* Port E data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define PESEL_ADDR 0xfffff423 /* Port E Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define PEDIR BYTE_REF(PEDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define PEDATA BYTE_REF(PEDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define PEPUEN BYTE_REF(PEPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define PESEL BYTE_REF(PESEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define PE(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define PE_CSA1 PE(1) /* Use CSA1 as PE(1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define PE_CSA2 PE(2) /* Use CSA2 as PE(2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define PE_CSA3 PE(3) /* Use CSA3 as PE(3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define PE_CSB0 PE(4) /* Use CSB0 as PE(4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define PE_CSB1 PE(5) /* Use CSB1 as PE(5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define PE_CSB2 PE(6) /* Use CSB2 as PE(6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define PE_CSB3 PE(7) /* Use CSB3 as PE(7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * Port F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define PFDATA_ADDR 0xfffff429 /* Port F data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define PFDIR BYTE_REF(PFDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define PFDATA BYTE_REF(PFDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define PFPUEN BYTE_REF(PFPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define PFSEL BYTE_REF(PFSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define PF(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define PF_A(x) PF((x) - 24) /* This is Port F specific only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define PF_A24 PF(0) /* Use A24 as PF(0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define PF_A25 PF(1) /* Use A25 as PF(1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define PF_A26 PF(2) /* Use A26 as PF(2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define PF_A27 PF(3) /* Use A27 as PF(3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define PF_A28 PF(4) /* Use A28 as PF(4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define PF_A29 PF(5) /* Use A29 as PF(5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define PF_A30 PF(6) /* Use A30 as PF(6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define PF_A31 PF(7) /* Use A31 as PF(7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * Port G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define PGDATA_ADDR 0xfffff431 /* Port G data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define PGDIR BYTE_REF(PGDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define PGDATA BYTE_REF(PGDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define PGPUEN BYTE_REF(PGPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define PGSEL BYTE_REF(PGSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define PG(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define PG_UART_TXD PG(0) /* Use UART_TXD as PG(0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define PG_UART_RXD PG(1) /* Use UART_RXD as PG(1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define PG_PWMOUT PG(2) /* Use PWMOUT as PG(2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define PG_TOUT2 PG(3) /* Use TOUT2 as PG(3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define PG_TIN2 PG(4) /* Use TIN2 as PG(4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define PG_TOUT1 PG(5) /* Use TOUT1 as PG(5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define PG_TIN1 PG(6) /* Use TIN1 as PG(6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define PG_RTCOUT PG(7) /* Use RTCOUT as PG(7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * Port J
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define PJDATA_ADDR 0xfffff439 /* Port J data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define PJSEL_ADDR 0xfffff43b /* Port J Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define PJDIR BYTE_REF(PJDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define PJDATA BYTE_REF(PJDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define PJSEL BYTE_REF(PJSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define PJ(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define PJ_CSD3 PJ(7) /* Use CSD3 as PJ(7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * Port K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define PKDATA_ADDR 0xfffff441 /* Port K data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define PKSEL_ADDR 0xfffff443 /* Port K Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define PKDIR BYTE_REF(PKDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define PKDATA BYTE_REF(PKDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define PKPUEN BYTE_REF(PKPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define PKSEL BYTE_REF(PKSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define PK(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * Port M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define PMDIR_ADDR 0xfffff438 /* Port M direction reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define PMDATA_ADDR 0xfffff439 /* Port M data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define PMPUEN_ADDR 0xfffff43a /* Port M Pull-Up enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define PMSEL_ADDR 0xfffff43b /* Port M Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define PMDIR BYTE_REF(PMDIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define PMDATA BYTE_REF(PMDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define PMPUEN BYTE_REF(PMPUEN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define PMSEL BYTE_REF(PMSEL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define PM(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * PWM Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define PWMC_ADDR 0xfffff500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define PWMC WORD_REF(PWMC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define PWMC_CLKSEL_MASK 0x0007 /* Clock Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define PWMC_CLKSEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define PWMC_PWMEN 0x0010 /* Enable PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define PMNC_POL 0x0020 /* PWM Output Bit Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define PWMC_PIN 0x0080 /* Current PWM output pin status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define PWMC_LOAD 0x0100 /* Force a new period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define PWMC_IRQEN 0x4000 /* Interrupt Request Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define PWMC_CLKSRC 0x8000 /* Clock Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define PWMC_EN PWMC_PWMEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * PWM Period Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define PWMP_ADDR 0xfffff502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define PWMP WORD_REF(PWMP_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * PWM Width Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define PWMW_ADDR 0xfffff504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define PWMW WORD_REF(PWMW_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * PWM Counter Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define PWMCNT_ADDR 0xfffff506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define PWMCNT WORD_REF(PWMCNT_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * 0xFFFFF6xx -- General-Purpose Timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * Timer Unit 1 and 2 Control Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define TCTL1_ADDR 0xfffff600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define TCTL1 WORD_REF(TCTL1_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define TCTL2_ADDR 0xfffff60c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define TCTL2 WORD_REF(TCTL2_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define TCTL_TEN 0x0001 /* Timer Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define TCTL_IRQEN 0x0010 /* IRQ Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define TCTL_OM 0x0020 /* Output Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define TCTL_FRR 0x0010 /* Free-Run Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define TCTL_ADDR TCTL1_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define TCTL TCTL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * Timer Unit 1 and 2 Prescaler Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define TPRER1_ADDR 0xfffff602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define TPRER1 WORD_REF(TPRER1_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define TPRER2_ADDR 0xfffff60e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define TPRER2 WORD_REF(TPRER2_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define TPRER_ADDR TPRER1_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define TPRER TPRER1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * Timer Unit 1 and 2 Compare Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define TCMP1_ADDR 0xfffff604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define TCMP1 WORD_REF(TCMP1_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define TCMP2_ADDR 0xfffff610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define TCMP2 WORD_REF(TCMP2_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define TCMP_ADDR TCMP1_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define TCMP TCMP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * Timer Unit 1 and 2 Capture Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define TCR1_ADDR 0xfffff606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define TCR1 WORD_REF(TCR1_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define TCR2_ADDR 0xfffff612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define TCR2 WORD_REF(TCR2_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define TCR_ADDR TCR1_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define TCR TCR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * Timer Unit 1 and 2 Counter Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define TCN1_ADDR 0xfffff608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define TCN1 WORD_REF(TCN1_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define TCN2_ADDR 0xfffff614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define TCN2 WORD_REF(TCN2_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define TCN_ADDR TCN1_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define TCN TCN1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * Timer Unit 1 and 2 Status Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define TSTAT1_ADDR 0xfffff60a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define TSTAT1 WORD_REF(TSTAT1_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define TSTAT2_ADDR 0xfffff616
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define TSTAT2 WORD_REF(TSTAT2_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define TSTAT_COMP 0x0001 /* Compare Event occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define TSTAT_CAPT 0x0001 /* Capture Event occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define TSTAT_ADDR TSTAT1_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define TSTAT TSTAT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * Watchdog Compare Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define WRR_ADDR 0xfffff61a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define WRR WORD_REF(WRR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * Watchdog Counter Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define WCN_ADDR 0xfffff61c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define WCN WORD_REF(WCN_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * Watchdog Control and Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define WCSR_ADDR 0xfffff618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define WCSR WORD_REF(WCSR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define WCSR_WDEN 0x0001 /* Watchdog Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define WCSR_FI 0x0002 /* Forced Interrupt (instead of SW reset)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define WCSR_WRST 0x0004 /* Watchdog Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * 0xFFFFF7xx -- Serial Peripheral Interface Slave (SPIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * SPI Slave Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define SPISR_ADDR 0xfffff700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define SPISR WORD_REF(SPISR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define SPISR_DATA_ADDR 0xfffff701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define SPISR_DATA BYTE_REF(SPISR_DATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define SPISR_DATA_MASK 0x00ff /* Shifted data from the external device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define SPISR_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define SPISR_SPISEN 0x0100 /* SPIS module enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define SPISR_POL 0x0200 /* SPSCLK polarity control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define SPISR_PHA 0x0400 /* Phase relationship between SPSCLK & SPSRxD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define SPISR_OVWR 0x0800 /* Data buffer has been overwritten */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define SPISR_DATARDY 0x1000 /* Data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define SPISR_ENPOL 0x2000 /* Enable Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define SPISR_IRQEN 0x4000 /* SPIS IRQ Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define SPISR_SPISIRQ 0x8000 /* SPIS IRQ posted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * SPIM Data Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define SPIMDATA_ADDR 0xfffff800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define SPIMDATA WORD_REF(SPIMDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * SPIM Control/Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define SPIMCONT_ADDR 0xfffff802
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define SPIMCONT WORD_REF(SPIMCONT_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define SPIMCONT_BIT_COUNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define SPIMCONT_SPIMIRQ 0x0080 /* Interrupt Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define SPIMCONT_XCH 0x0100 /* Exchange */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define SPIMCONT_RSPIMEN 0x0200 /* Enable SPIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define SPIMCONT_DATA_RATE_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define SPIMCONT_IRQ SPIMCONT_SPIMIRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define SPIMCONT_ENABLE SPIMCONT_SPIMEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * 0xFFFFF9xx -- UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * UART Status/Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define USTCNT_ADDR 0xfffff900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define USTCNT WORD_REF(USTCNT_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define USTCNT_TXAVAILEN 0x0001 /* Transmitter Available Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define USTCNT_TXHALFEN 0x0002 /* Transmitter Half Empty Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define USTCNT_TXEMPTYEN 0x0004 /* Transmitter Empty Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define USTCNT_RXREADYEN 0x0008 /* Receiver Ready Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define USTCNT_RXHALFEN 0x0010 /* Receiver Half-Full Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define USTCNT_RXFULLEN 0x0020 /* Receiver Full Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define USTCNT_CTSDELTAEN 0x0040 /* CTS Delta Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define USTCNT_GPIODELTAEN 0x0080 /* Old Data Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define USTCNT_STOP 0x0200 /* Stop bit transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define USTCNT_ODD_EVEN 0x0400 /* Odd Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define USTCNT_PARITYEN 0x0800 /* Parity Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define USTCNT_CLKMODE 0x1000 /* Clock Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define USTCNT_TXEN 0x2000 /* Transmitter Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define USTCNT_RXEN 0x4000 /* Receiver Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define USTCNT_UARTEN 0x8000 /* UART Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define USTCNT_TXAE USTCNT_TXAVAILEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define USTCNT_TXHE USTCNT_TXHALFEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define USTCNT_TXEE USTCNT_TXEMPTYEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define USTCNT_RXRE USTCNT_RXREADYEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define USTCNT_RXHE USTCNT_RXHALFEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define USTCNT_RXFE USTCNT_RXFULLEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define USTCNT_CTSD USTCNT_CTSDELTAEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define USTCNT_ODD USTCNT_ODD_EVEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define USTCNT_PEN USTCNT_PARITYEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define USTCNT_CLKM USTCNT_CLKMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define USTCNT_UEN USTCNT_UARTEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * UART Baud Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define UBAUD_ADDR 0xfffff902
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define UBAUD WORD_REF(UBAUD_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define UBAUD_PRESCALER_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define UBAUD_DIVIDE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define UBAUD_GPIOSRC 0x1000 /* GPIO source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define UBAUD_GPIODIR 0x2000 /* GPIO Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define UBAUD_GPIO 0x4000 /* Current GPIO pin status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define UBAUD_GPIODELTA 0x8000 /* GPIO pin value changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * UART Receiver Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define URX_ADDR 0xfffff904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define URX WORD_REF(URX_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define URX_RXDATA_ADDR 0xfffff905
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define URX_RXDATA_MASK 0x00ff /* Received data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define URX_RXDATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define URX_PARITY_ERROR 0x0100 /* Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define URX_BREAK 0x0200 /* Break Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define URX_FRAME_ERROR 0x0400 /* Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define URX_OVRUN 0x0800 /* Serial Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define URX_FIFO_FULL 0x8000 /* FIFO is Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * UART Transmitter Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define UTX_ADDR 0xfffff906
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define UTX WORD_REF(UTX_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define UTX_TXDATA_ADDR 0xfffff907
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define UTX_TXDATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define UTX_CTS_DELTA 0x0100 /* CTS changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define UTX_CTS_STATUS 0x0200 /* CTS State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define UTX_IGNORE_CTS 0x0800 /* Ignore CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define UTX_CTS_STAT UTX_CTS_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define UTX_NOCTS UTX_IGNORE_CTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * UART Miscellaneous Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define UMISC_ADDR 0xfffff908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define UMISC WORD_REF(UMISC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define UMISC_TX_POL 0x0004 /* Transmit Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define UMISC_RX_POL 0x0008 /* Receive Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define UMISC_RTS 0x0040 /* Set RTS status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define UMISC_RTSCONT 0x0080 /* Choose RTS control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define UMISC_CLKSRC 0x4000 /* Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* generalization of uart control registers to support multiple ports: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) typedef volatile struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) volatile unsigned short int ustcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) volatile unsigned short int ubaud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) volatile unsigned short int w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) volatile unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) volatile unsigned char rxdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) } urx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) volatile unsigned short int w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) volatile unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) volatile unsigned char txdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) } utx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) volatile unsigned short int umisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) volatile unsigned short int pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) volatile unsigned short int pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) volatile unsigned short int pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) } __packed m68328_uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * 0xFFFFFAxx -- LCD Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * LCD Screen Starting Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define LSSA_ADDR 0xfffffa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define LSSA LONG_REF(LSSA_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define LSSA_SSA_MASK 0xfffffffe /* Bit 0 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * LCD Virtual Page Width Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define LVPW_ADDR 0xfffffa05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define LVPW BYTE_REF(LVPW_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * LCD Screen Width Register (not compatible with 'EZ328 !!!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define LXMAX_ADDR 0xfffffa08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define LXMAX WORD_REF(LXMAX_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define LXMAX_XM_MASK 0x02ff /* Bits 0-3 are reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * LCD Screen Height Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define LYMAX_ADDR 0xfffffa0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define LYMAX WORD_REF(LYMAX_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define LYMAX_YM_MASK 0x02ff /* Bits 10-15 are reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * LCD Cursor X Position Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define LCXP_ADDR 0xfffffa18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define LCXP WORD_REF(LCXP_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define LCXP_CC_MASK 0xc000 /* Cursor Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define LCXP_CC_TRAMSPARENT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define LCXP_CC_BLACK 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define LCXP_CC_REVERSED 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define LCXP_CC_WHITE 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define LCXP_CXP_MASK 0x02ff /* Cursor X position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * LCD Cursor Y Position Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define LCYP_ADDR 0xfffffa1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define LCYP WORD_REF(LCYP_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * LCD Cursor Width and Heigth Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define LCWCH_ADDR 0xfffffa1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define LCWCH WORD_REF(LCWCH_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define LCWCH_CH_MASK 0x001f /* Cursor Height */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define LCWCH_CH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define LCWCH_CW_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * LCD Blink Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define LBLKC_ADDR 0xfffffa1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define LBLKC BYTE_REF(LBLKC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define LBLKC_BD_MASK 0x7f /* Blink Divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define LBLKC_BD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define LBLKC_BKEN 0x80 /* Blink Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * LCD Panel Interface Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define LPICF_ADDR 0xfffffa20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define LPICF BYTE_REF(LPICF_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define LPICF_GS_MASK 0x01 /* Gray-Scale Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define LPICF_GS_BW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define LPICF_GS_GRAY_4 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define LPICF_PBSIZ_MASK 0x06 /* Panel Bus Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define LPICF_PBSIZ_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define LPICF_PBSIZ_2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define LPICF_PBSIZ_4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * LCD Polarity Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define LPOLCF_ADDR 0xfffffa21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define LPOLCF BYTE_REF(LPOLCF_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * LACD (LCD Alternate Crystal Direction) Rate Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define LACDRC_ADDR 0xfffffa23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define LACDRC BYTE_REF(LACDRC_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define LACDRC_ACD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * LCD Pixel Clock Divider Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define LPXCD_ADDR 0xfffffa25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define LPXCD BYTE_REF(LPXCD_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define LPXCD_PCD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * LCD Clocking Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define LCKCON_ADDR 0xfffffa27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define LCKCON BYTE_REF(LCKCON_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define LCKCON_PCDS 0x01 /* Pixel Clock Divider Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define LCKCON_DWIDTH 0x02 /* Display Memory Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define LCKCON_DWS_MASK 0x3c /* Display Wait-State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define LCKCON_DWS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define LCKCON_DMA16 0x40 /* DMA burst length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define LCKCON_LCDON 0x80 /* Enable LCD Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define LCKCON_DW_MASK LCKCON_DWS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * LCD Last Buffer Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define LLBAR_ADDR 0xfffffa29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define LLBAR BYTE_REF(LLBAR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define LLBAR_LBAR_MASK 0x7f /* Number of memory words to fill 1 line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define LLBAR_LBAR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * LCD Octet Terminal Count Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define LOTCR_ADDR 0xfffffa2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define LOTCR BYTE_REF(LOTCR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * LCD Panning Offset Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define LPOSR_ADDR 0xfffffa2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define LPOSR BYTE_REF(LPOSR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define LPOSR_BOS 0x08 /* Byte offset (for B/W mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define LPOSR_POS_MASK 0x07 /* Pixel Offset Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define LPOSR_POS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * LCD Frame Rate Control Modulation Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define LFRCM_ADDR 0xfffffa31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define LFRCM BYTE_REF(LFRCM_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define LFRCM_YMOD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define LFRCM_XMOD_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * LCD Gray Palette Mapping Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define LGPMR_ADDR 0xfffffa32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define LGPMR WORD_REF(LGPMR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define LGPMR_GLEVEL3_MASK 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define LGPMR_GLEVEL3_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define LGPMR_GLEVEL2_MASK 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define LGPMR_GLEVEL2_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define LGPMR_GLEVEL0_MASK 0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define LGPMR_GLEVEL0_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define LGPMR_GLEVEL1_MASK 0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define LGPMR_GLEVEL1_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /**********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * 0xFFFFFBxx -- Real-Time Clock (RTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * RTC Hours Minutes and Seconds Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define RTCTIME_ADDR 0xfffffb00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define RTCTIME LONG_REF(RTCTIME_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define RTCTIME_SECONDS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define RTCTIME_MINUTES_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define RTCTIME_HOURS_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * RTC Alarm Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define RTCALRM_ADDR 0xfffffb04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define RTCALRM LONG_REF(RTCALRM_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define RTCALRM_SECONDS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define RTCALRM_MINUTES_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define RTCALRM_HOURS_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * RTC Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define RTCCTL_ADDR 0xfffffb0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define RTCCTL WORD_REF(RTCCTL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define RTCCTL_384 0x0020 /* Crystal Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define RTCCTL_ENABLE 0x0080 /* RTC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* 'EZ328-compatible definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define RTCCTL_XTL RTCCTL_384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define RTCCTL_EN RTCCTL_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * RTC Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define RTCISR_ADDR 0xfffffb0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define RTCISR WORD_REF(RTCISR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define RTCISR_SW 0x0001 /* Stopwatch timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * RTC Interrupt Enable Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define RTCIENR_ADDR 0xfffffb10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define RTCIENR WORD_REF(RTCIENR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * Stopwatch Minutes Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define STPWCH_ADDR 0xfffffb12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define STPWCH WORD_REF(STPWCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define STPWCH_CNT_MASK 0x00ff /* Stopwatch countdown value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define SPTWCH_CNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #endif /* _MC68328_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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