^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) M68000 Hi-Performance Microprocessor Division
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) M68060 Software Package
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Production Release P1.00 -- October 10, 1994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) THE SOFTWARE is provided on an "AS IS" basis and without warranty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) To the maximum extent permitted by applicable law,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) and any warranty against infringement with regard to the SOFTWARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) (INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) To the maximum extent permitted by applicable law,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) so long as this entire notice is retained without alteration in any modified and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) redistributed versions, and that such modified versions are clearly identified as such.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) No licenses are granted by implication, estoppel or otherwise under any patents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) or trademarks of Motorola, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) CHANGES SINCE LAST RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 1) "movep" emulation where data was being read from memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) was reading the intermediate bytes. Emulation now only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) reads the required bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 2) "flogn", "flog2", and "flog10" of "1" was setting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Inexact FPSR bit. Emulation now does not set Inexact for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 3) For an opclass three FP instruction where the effective addressing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) mode was pre-decrement or post-increment and the address register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) was A0 or A1, the address register was not being updated as a result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) of the operation. This has been corrected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 4) Beta B.2 version had the following erratum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Scenario:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) If {i,d}mem_{read,write}_{byte,word,long}() returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) a failing value to the 68060SP, the package ignores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) this return value and continues with program execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) as if it never received a failing value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Effect:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) -------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) For example, if a user executed "fsin.x ADDR,fp0" where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ADDR should cause a "segmentation violation", the memory read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) requested by the package should return a failing value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) to the package. Since the package currently ignores this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return value, the user program will continue to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) next instruction, and the result created in fp0 will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) undefined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) Fix:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) This has been fixed in the current release.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) Upon receiving a non-zero (failing) return value from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) a {i,d}mem_{read,write}_{byte,word,long}() "call-out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) the package creates a 16-byte access error stack frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) from the current exception stack frame and exits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) through the "call-out" _real_access(). This is the process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) as described in the MC68060 User's Manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) For instruction read access errors, the info stacked is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SR = SR at time of exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PC = PC of instruction being emulated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) VOFF = $4008 (stack frame format type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ADDRESS = PC of instruction being emulated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FSLW = FAULT STATUS LONGWORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) The valid FSLW bits are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) bit 27 = 1 (misaligned bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bit 24 = 1 (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) bit 23 = 0 (write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bit 22:21 = 10 (SIZE = word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bit 20:19 = 00 (TT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bit 18:16 = x10 (TM; x = 1 for supervisor mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) bit 15 = 1 (IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bit 0 = 1 (Software Emulation Error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) all other bits are EQUAL TO ZERO and can be set by the _real_access()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "call-out" stub by the user as appropriate. The MC68060 User's Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) stated that ONLY "bit 0" would be set. The 060SP attempts to set a few
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) other bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) For data read/write access errors, the info stacked is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SR = SR at time of exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PC = PC of instruction being emulated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) VOFF = $4008 (stack frame format type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ADDRESS = Address of source or destination operand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) FSLW = FAULT STATUS LONGWORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) The valid FSLW bits are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bit 27 = 0 (misaligned bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bit 24 = x (read; 1 if read, 0 if write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bit 23 = x (write; 1 if write, 0 if read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bit 22:21 = xx (SIZE; see MC68060 User's Manual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) bit 20:19 = 00 (TT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bit 18:16 = x01 (TM; x = 1 for supervisor mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bit 15 = 0 (IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bit 0 = 1 (Software Emulation Error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) all other bits are EQUAL TO ZERO and can be set by the _real_access()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "call-out" stub by the user as appropriate. The MC68060 User's Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) stated that ONLY "bit 0" would be set. The 060SP attempts to set a few
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) other bits.
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