Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) |	x_ovfl.sa 3.5 7/1/91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) |	fpsp_ovfl --- FPSP handler for overflow exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) |	Overflow occurs when a floating-point intermediate result is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) |	too large to be represented in a floating-point data register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) |	or when storing to memory, the contents of a floating-point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) |	data register are too large to be represented in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) |	destination format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) | Trap disabled results
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) | If the instruction is move_out, then garbage is stored in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) | destination.  If the instruction is not move_out, then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) | destination is not affected.  For 68881 compatibility, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) | following values should be stored at the destination, based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) | on the current rounding mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) |  RN	Infinity with the sign of the intermediate result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) |  RZ	Largest magnitude number, with the sign of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) |	intermediate result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) |  RM   For pos overflow, the largest pos number. For neg overflow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) |	-infinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) |  RP   For pos overflow, +infinity. For neg overflow, the largest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) |	neg number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) | Trap enabled results
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) | All trap disabled code applies.  In addition the exceptional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) | operand needs to be made available to the users exception handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) | with a bias of $6000 subtracted from the exponent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) |		Copyright (C) Motorola, Inc. 1990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) |			All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) |       For details on the license for this file, please see the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) |       file, README, in this same directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) X_OVFL:	|idnt    2,1 | Motorola 040 Floating Point Software Package
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	|section	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include "fpsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	|xref	ovf_r_x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	|xref	ovf_r_x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	|xref	store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	|xref	real_ovfl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	|xref	real_inex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	|xref	fpsp_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	|xref	g_opcls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	|xref	b1238_fix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.global	fpsp_ovfl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) fpsp_ovfl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	link		%a6,#-LOCAL_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	fsave		-(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	moveml		%d0-%d1/%a0-%a1,USER_DA(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	fmovemx	%fp0-%fp3,USER_FP0(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	fmoveml	%fpcr/%fpsr/%fpiar,USER_FPCR(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) |	The 040 doesn't set the AINEX bit in the FPSR, the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) |	line temporarily rectifies this error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	bsetb	#ainex_bit,FPSR_AEXCEPT(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	bsrl	ovf_adj		|denormalize, round & store interm op
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) |	if overflow traps not enabled check for inexact exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	btstb	#ovfl_bit,FPCR_ENABLE(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	beqs	ck_inex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	btstb		#E3,E_BYTE(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	beqs		no_e3_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	bfextu		CMDREG3B(%a6){#6:#3},%d0	|get dest reg no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	bclrb		%d0,FPR_DIRTY_BITS(%a6)	|clr dest dirty bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	bsrl		b1238_fix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	movel		USER_FPSR(%a6),FPSR_SHADOW(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	orl		#sx_mask,E_BYTE(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) no_e3_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	moveml		USER_DA(%a6),%d0-%d1/%a0-%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	fmovemx	USER_FP0(%a6),%fp0-%fp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	fmoveml	USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	frestore	(%a7)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unlk		%a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	bral		real_ovfl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) | It is possible to have either inex2 or inex1 exceptions with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) | ovfl.  If the inex enable bit is set in the FPCR, and either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) | inex2 or inex1 occurred, we must clean up and branch to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) | real inex handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) ck_inex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) |	move.b		FPCR_ENABLE(%a6),%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) |	and.b		FPSR_EXCEPT(%a6),%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) |	andi.b		#$3,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	btstb		#inex2_bit,FPCR_ENABLE(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	beqs		ovfl_exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) | Inexact enabled and reported, and we must take an inexact exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) take_inex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	btstb		#E3,E_BYTE(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	beqs		no_e3_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	bfextu		CMDREG3B(%a6){#6:#3},%d0	|get dest reg no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	bclrb		%d0,FPR_DIRTY_BITS(%a6)	|clr dest dirty bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	bsrl		b1238_fix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	movel		USER_FPSR(%a6),FPSR_SHADOW(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	orl		#sx_mask,E_BYTE(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) no_e3_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	moveb		#INEX_VEC,EXC_VEC+1(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	moveml		USER_DA(%a6),%d0-%d1/%a0-%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	fmovemx	USER_FP0(%a6),%fp0-%fp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	fmoveml	USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	frestore	(%a7)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	unlk		%a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	bral		real_inex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ovfl_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	bclrb	#E3,E_BYTE(%a6)	|test and clear E3 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	beqs	e1_set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) | Clear dirty bit on dest resister in the frame before branching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) | to b1238_fix.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	bfextu		CMDREG3B(%a6){#6:#3},%d0	|get dest reg no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	bclrb		%d0,FPR_DIRTY_BITS(%a6)	|clr dest dirty bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	bsrl		b1238_fix		|test for bug1238 case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	movel		USER_FPSR(%a6),FPSR_SHADOW(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	orl		#sx_mask,E_BYTE(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	moveml		USER_DA(%a6),%d0-%d1/%a0-%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	fmovemx	USER_FP0(%a6),%fp0-%fp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	fmoveml	USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	frestore	(%a7)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	unlk		%a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	bral		fpsp_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) e1_set:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	moveml		USER_DA(%a6),%d0-%d1/%a0-%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	fmovemx	USER_FP0(%a6),%fp0-%fp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	fmoveml	USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	unlk		%a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	bral		fpsp_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) |	ovf_adj
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ovf_adj:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) | Have a0 point to the correct operand.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	btstb	#E3,E_BYTE(%a6)	|test E3 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	beqs	ovf_e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	lea	WBTEMP(%a6),%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	bras	ovf_com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ovf_e1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	lea	ETEMP(%a6),%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ovf_com:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	bclrb	#sign_bit,LOCAL_EX(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	sne	LOCAL_SGN(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	bsrl	g_opcls		|returns opclass in d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	cmpiw	#3,%d0		|check for opclass3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	bnes	not_opc011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) | FPSR_CC is saved and restored because ovf_r_x3 affects it. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) | CCs are defined to be 'not affected' for the opclass3 instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	moveb	FPSR_CC(%a6),L_SCR1(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	bsrl	ovf_r_x3	|returns a0 pointing to result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	moveb	L_SCR1(%a6),FPSR_CC(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	bral	store		|stores to memory or register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) not_opc011:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	bsrl	ovf_r_x2	|returns a0 pointing to result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	bral	store		|stores to memory or register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	|end