^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) | x_fline.sa 3.3 1/10/91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) | fpsp_fline --- FPSP handler for fline exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) | First determine if the exception is one of the unimplemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) | floating point instructions. If so, let fpsp_unimp handle it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) | Next, determine if the instruction is an fmovecr with a non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) | <ea> field. If so, handle here and return. Otherwise, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) | must be a real F-line exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) | Copyright (C) Motorola, Inc. 1990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) | All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) | For details on the license for this file, please see the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) | file, README, in this same directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) X_FLINE: |idnt 2,1 | Motorola 040 Floating Point Software Package
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) |section 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "fpsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) |xref real_fline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) |xref fpsp_unimp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) |xref uni_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) |xref mem_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) |xref fpsp_fmt_error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .global fpsp_fline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) fpsp_fline:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) | check for unimplemented vector first. Use EXC_VEC-4 because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) | the equate is valid only after a 'link a6' has pushed one more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) | long onto the stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) cmpw #UNIMP_VEC,EXC_VEC-4(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) beql fpsp_unimp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) | fmovecr with non-zero <ea> handling here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) subl #4,%a7 |4 accounts for 2-word difference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) | ;between six word frame (unimp) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) | ;four word frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) link %a6,#-LOCAL_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) fsave -(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) moveml %d0-%d1/%a0-%a1,USER_DA(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) moveal EXC_PC+4(%a6),%a0 |get address of fline instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) leal L_SCR1(%a6),%a1 |use L_SCR1 as scratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) movel #4,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) addl #4,%a6 |to offset the sub.l #4,a7 above so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) | ;a6 can point correctly to the stack frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) | ;before branching to mem_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) bsrl mem_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) subl #4,%a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) movel L_SCR1(%a6),%d0 |d0 contains the fline and command word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bfextu %d0{#4:#3},%d1 |extract coprocessor id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) cmpib #1,%d1 |check if cpid=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bne not_mvcr |exit if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bfextu %d0{#16:#6},%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cmpib #0x17,%d1 |check if it is an FMOVECR encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) bne not_mvcr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) | ;if an FMOVECR instruction, fix stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) | ;and go to FPSP_UNIMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) fix_stack:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) cmpib #VER_40,(%a7) |test for orig unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) bnes ck_rev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) subl #UNIMP_40_SIZE-4,%a7 |emulate an orig fsave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) moveb #VER_40,(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) moveb #UNIMP_40_SIZE-4,1(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clrw 2(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) bras fix_con
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ck_rev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) cmpib #VER_41,(%a7) |test for rev unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bnel fpsp_fmt_error |if not $40 or $41, exit with error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) subl #UNIMP_41_SIZE-4,%a7 |emulate a rev fsave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) moveb #VER_41,(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) moveb #UNIMP_41_SIZE-4,1(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clrw 2(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) fix_con:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) movew EXC_SR+4(%a6),EXC_SR(%a6) |move stacked sr to new position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) movel EXC_PC+4(%a6),EXC_PC(%a6) |move stacked pc to new position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) fmovel EXC_PC(%a6),%FPIAR |point FPIAR to fline inst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) movel #4,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) addl %d1,EXC_PC(%a6) |increment stacked pc value to next inst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) movew #0x202c,EXC_VEC(%a6) |reformat vector to unimp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) clrl EXC_EA(%a6) |clear the EXC_EA field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) movew %d0,CMDREG1B(%a6) |move the lower word into CMDREG1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clrl E_BYTE(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) bsetb #UFLAG,T_BYTE(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) moveml USER_DA(%a6),%d0-%d1/%a0-%a1 |restore data registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) bral uni_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) not_mvcr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) moveml USER_DA(%a6),%d0-%d1/%a0-%a1 |restore data registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) frestore (%a7)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unlk %a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) addl #4,%a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bral real_fline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) |end
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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